View Z8F2402AR020EC_5103173.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product specification z8f640x, z8f480x, z8f320x, z8f240x, and z8f160x z8 encore! ? microcontrollers with flash memory and 10-bit a/d converter ps017611-0406 zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558.8300 ? www.zilog.com
ps017611-0406 this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to reques t copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com document disclaimer zilog is a registered trademark of zilog inc. in th e united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ?2004 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devices sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantabi lity or fitness for any purpose except with the express written approval of zilog, use of informati on, devices, or technology as critical components of life support systems is not authorized. no licens es are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? iii table of contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ez8 cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . 4 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 system and short resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 watch-dog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? iv external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 stop mode recovery using watch-dog timer time-out . . . . . . . 29 stop mode recovery using a gpio port pin transition . . . . . . . . 30 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 port a-h address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port a-h control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 port a-h input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port a-h output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 interrupt assertion types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 48 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . 51 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . 52 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . 53 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 interrupt port select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? v timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . 66 timer output signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 timer 0-3 high and low byte registers . . . . . . . . . . . . . . . . . . . . 66 timer reload high and low byte registers . . . . . . . . . . . . . . . . . 67 timer 0-3 pwm high and low byte registers . . . . . . . . . . . . . . . 69 timer 0-3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 watch-dog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 watch-dog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 watch-dog timer time-out response . . . . . . . . . . . . . . . . . . . . . 73 watch-dog timer reload unlock sequence . . . . . . . . . . . . . . . . . 74 watch-dog timer control register definitions . . . . . . . . . . . . . . . . . . 75 watch-dog timer control register . . . . . . . . . . . . . . . . . . . . . . . . 75 watch-dog timer reload upper, high and low byte registers . 76 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 transmitting data using the polled method . . . . . . . . . . . . . . . . . . 80 transmitting data using the interrupt-d riven method . . . . . . . . . . 81 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . 82 receiving data using the interrupt-dri ven method . . . . . . . . . . . . 82 receiving data using th e direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 uartx transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 uartx receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 uartx status 0 and status 1 registers . . . . . . . . . . . . . . . . . . . . . 87 uartx control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . 89 uartx baud rate high and low byte registers . . . . . . . . . . . . . 91 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? vi transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 infrared encoder/decoder control register definitions . . . . . . . . . . . . 98 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 spi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 spi clock phase and polarity control . . . . . . . . . . . . . . . . . . . . . 102 multi-master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 spi baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 spi control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 spi mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 spi baud rate high and low byte registers . . . . . . . . . . . . . . . 110 i2c controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 sda and scl signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 i 2 c interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 writing a transaction with a 7-bit address . . . . . . . . . . . . . . . . . 112 writing a transaction with a 10-bit addr ess . . . . . . . . . . . . . . . . 114 reading a transaction with a 7-bit address . . . . . . . . . . . . . . . . 115 reading a transaction with a 10-bit address . . . . . . . . . . . . . . . 116 i2c control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 i2c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 i2c status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 i2c control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 i2c baud rate high and low byte registers . . . . . . . . . . . . . . . 121 direct memory access controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 dma0 and dma1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 configuring dma0 and dma1 for data transfer . . . . . . . . . . . . 123
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? vii dma_adc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 configuring dma_adc for data transfer . . . . . . . . . . . . . . . . . 124 dma control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 dmax control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 dmax i/o address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 dmax address high nibble register . . . . . . . . . . . . . . . . . . . . . 126 dmax start/current address low byte register . . . . . . . . . . . . 127 dmax end address low byte register . . . . . . . . . . . . . . . . . . . 128 dma_adc address register . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 dma_adc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 dma status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 automatic power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 dma control of the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 adc control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 flash operation timing using the flash frequency registers . . 141 flash code protection against external access . . . . . . . . . . . . . . 141 flash code protection against acci dental program and erasure 141 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 flash frequency high and low byte re gisters . . . . . . . . . . . . . . 147
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? viii option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . 148 option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . 149 program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . 150 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . 154 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 watchpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 on-chip debugger control register defin itions . . . . . . . . . . . . . . . . 161 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 ocd watchpoint control register . . . . . . . . . . . . . . . . . . . . . . . . 163 ocd watchpoint address register . . . . . . . . . . . . . . . . . . . . . . . 164 ocd watchpoint data register . . . . . . . . . . . . . . . . . . . . . . . . . . 164 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 20mhz crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . 165 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . 173 general purpose i/o port input data sample timing . . . . . . . . . 176 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . 177 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 assembly language programming introduc tion . . . . . . . . . . . . . . . . . 182
ps017611-0406 table of contents z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ix assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 document information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 document number description . . . . . . . . . . . . . . . . . . . . . . . . . . 215 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
ps017611-0406 list of figures z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xiv list of figures figure 1. z8 encore! ? block diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. z8fxx01 in 40-pin dual inlin e package (dip) . . . . . . . . . . 7 figure 3. z8fxx01 in 44-pin plastic leaded chip carrier (plcc) . . 8 figure 4. z8fxx01 in 44-pin low-pr ofile quad flat package (lqfp) 9 figure 5. z8fxx02 in 64-pin low-pr ofile quad flat package (lqfp) 10 figure 6. z8fxx02 in 68-pin plastic leaded chip carrier (plcc) . 11 figure 7. z8fxx03 in 80-pin quad flat package (qfp) . . . . . . . . . . 12 figure 8. power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. voltage brown-out reset operation . . . . . . . . . . . . . . . . . 28 figure 10. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. interrupt controller block diag ram . . . . . . . . . . . . . . . . . 46 figure 12. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 13. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 14. uart asynchronous data format without parity . . . . . . 80 figure 15. uart asynchronous data format with parity . . . . . . . . . 80 figure 16. uart asynchronous multiprocessor (9-bit) mode data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 17. infrared data communication system block diagram . . . 95 figure 18. infrared data transmission . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 19. infrared data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 20. spi configured as a master in a single master, single slave system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 21. spi configured as a master in a single master, multiple slave system . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 22. spi configured as a slave . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 23. spi timing when phase is 0 . . . . . . . . . . . . . . . . . . . . 103 figure 24. spi timing when phase is 1 . . . . . . . . . . . . . . . . . . . . 104 figure 25. 7-bit addressed slave data transfer format . . . . . . . . . 113 figure 26. 10-bit addressed slave data transfer format . . . . . . . . 114 figure 27. receive data transfer format for a 7-bit addressed slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 28. receive data format for a 10-bit addressed slave . . . . 116 figure 29. analog-to-digital converter block diagram . . . . . . . . . 133 figure 30. flash memory arrangement . . . . . . . . . . . . . . . . . . . . . . 139
ps017611-0406 list of figures z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xv figure 31. flash controller operation flow chart . . . . . . . . . . . . . . 140 figure 32. on-chip debugger block diag ram . . . . . . . . . . . . . . . . . 151 figure 33. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 34. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 35. ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 36. recommended crystal oscillator configuration (20mhz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 37. nominal icc versus system clock frequency . . . . . . . 170 figure 38. nominal halt mode icc versus system clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 39. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 40. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 41. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . 178 figure 42. spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 43. spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 44. i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 figure 45. flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 46. opcode map cell description . . . . . . . . . . . . . . . . . . . . . 202 figure 47. first opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 48. second opcode map after 1fh . . . . . . . . . . . . . . . . . . . . 205 figure 49. 40-lead plastic dual-inline package (pdip) . . . . . . . . . 206 figure 50. 44-lead low-profile quad flat package (lqfp) . . . . . . 207 figure 51. 44-lead plastic lead chip carrier package (plcc) . . . 207 figure 52. 64-lead low-profile quad flat package (lqfp) . . . . . . 208 figure 53. 68-lead plastic lead chip carrier package (plcc) . . . 209 figure 54. 80-lead quad-flat package (qfp) . . . . . . . . . . . . . . . . . 210
ps017611-0406 list of tables z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? x list of tables table 1. z8f640x family part selection guide . . . . . . . . . . . . . . . . 2 table 2. z8f640x family package options . . . . . . . . . . . . . . . . . . . 6 table 3. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. pin characteristics of the z8f640x family . . . . . . . . . . . . 15 table 5. z8f640x family program memory maps . . . . . . . . . . . . . 18 table 6. z8f640x family data memory ma ps . . . . . . . . . . . . . . . . 19 table 7. register file address map . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. reset and stop mode recovery characteristics and latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. reset sources and resulting reset type . . . . . . . . . . . . . . 26 table 10. stop mode recovery sources and resulting action . . . 29 table 11. port availability by device and package type . . . . . . . . . 33 table 12. port alternate function mapping . . . . . . . . . . . . . . . . . . . 35 table 13. port a-h gpio address registers (pxaddr) . . . . . . . . . 37 table 14. gpio port registers and sub-registers . . . . . . . . . . . . . . 37 table 15. port a-h control registers (pxctl) . . . . . . . . . . . . . . . . 38 table 16. port a-h data direction sub-registers . . . . . . . . . . . . . . . 39 table 17. port a-h alternate function sub-registers . . . . . . . . . . . 39 table 18. port a-h output control sub-registers . . . . . . . . . . . . . . 40 table 19. port a-h high drive enable su b-registers . . . . . . . . . . . 41 table 20. port a-h input data registers (pxin) . . . . . . . . . . . . . . . . 42 table 21. port a-h stop mode recovery source enable sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22. port a-h output data register (pxout) . . . . . . . . . . . . . 43 table 23. interrupt vectors in order of priority . . . . . . . . . . . . . . . . 45 table 24. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . 48 table 25. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . 49 table 26. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . 50 table 27. irq0 enable and priority encoding . . . . . . . . . . . . . . . . . 51 table 28. irq0 enable high bit register (irq0enh) . . . . . . . . . . 51 table 29. irq0 enable low bit register (irq0enl) . . . . . . . . . . . 52 table 30. irq1 enable and priority encoding . . . . . . . . . . . . . . . . . 52 table 31. irq1 enable low bit register (irq1enl) . . . . . . . . . . . 53
ps017611-0406 list of tables z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xi table 32. irq2 enable and priority encoding . . . . . . . . . . . . . . . . . 53 table 33. irq1 enable high bit register (irq1enh) . . . . . . . . . . 53 table 34. irq2 enable low bit register (irq2enl) . . . . . . . . . . . 54 table 35. irq2 enable high bit register (irq2enh) . . . . . . . . . . 54 table 36. interrupt edge select register (irqes) . . . . . . . . . . . . . . 55 table 37. interrupt port select register (irqps) . . . . . . . . . . . . . . . 55 table 38. interrupt control register (irqctl) . . . . . . . . . . . . . . . . 56 table 39. timer 0-3 high byte register (txh) . . . . . . . . . . . . . . . . 67 table 40. timer 0-3 low byte register (txl) . . . . . . . . . . . . . . . . . 67 table 41. timer 0-3 reload high byte register (txrh) . . . . . . . . . 68 table 42. timer 0-3 reload low byte register (txrl) . . . . . . . . . . 68 table 43. timer 0-3 pwm high byte register (txpwmh) . . . . . . 69 table 44. timer 0-3 pwm low byte register (txpwml) . . . . . . . 69 table 45. timer 0-3 control register (txctl) . . . . . . . . . . . . . . . . 70 table 46. watch-dog timer approximate time-out delays . . . . . . 73 table 47. watch-dog timer control register (wdtctl) . . . . . . . 75 table 48. watch-dog timer reload upper byte register (wdtu) 76 table 49. watch-dog timer reload high byte register (wdth) . 76 table 50. watch-dog timer reload low byte register (wdtl) . . 77 table 51. uartx transmit data register (uxtxd) . . . . . . . . . . . . 86 table 52. uartx receive data register (uxrxd) . . . . . . . . . . . . . 87 table 53. uartx status 0 register (uxstat0) . . . . . . . . . . . . . . . 87 table 54. uartx control 0 register (uxctl0) . . . . . . . . . . . . . . . 89 table 55. uartx status 1 register (uxstat1) . . . . . . . . . . . . . . . 89 table 56. uartx control 1 register (uxctl1) . . . . . . . . . . . . . . . 90 table 57. uartx baud rate high byte register (uxbrh) . . . . . . 91 table 58. uartx baud rate low byte register (uxbrl) . . . . . . . 92 table 59. uart baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 60. spi clock phase (phase) and clock polarity (clkpol) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 61. spi data register (spidata) . . . . . . . . . . . . . . . . . . . . 106 table 62. spi control register (spictl) . . . . . . . . . . . . . . . . . . . . 107 table 63. spi status register (spistat) . . . . . . . . . . . . . . . . . . . . 108 table 64. spi mode register (spimode) . . . . . . . . . . . . . . . . . . . 109 table 65. spi baud rate high byte register (spibrh) . . . . . . . . 110 table 66. spi baud rate low byte register (spibrl) . . . . . . . . . 110
ps017611-0406 list of tables z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xii table 67. i2c data register (i2cdata) . . . . . . . . . . . . . . . . . . . . 118 table 68. i2c status register (i2cstat) . . . . . . . . . . . . . . . . . . . . 118 table 69. i2c control register (i2cctl) . . . . . . . . . . . . . . . . . . . . 119 table 70. i2c baud rate high byte register (i2cbrh) . . . . . . . . 121 table 71. i2c baud rate low byte register (i2cbrl) . . . . . . . . . 121 table 72. dmax control register (dmaxc tl) . . . . . . . . . . . . . . 124 table 73. dmax i/o address register (dmaxio) . . . . . . . . . . . . 126 table 74. dmax address high nibble register (dmaxh) . . . . . . 126 table 75. dmax end address low byte register (dmaxend) . 128 table 76. dmax start/current address low byte register (dmaxstart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 77. dma_adc register file address example . . . . . . . . . . 129 table 78. dma_adc address register (dmaa_addr) . . . . . . 129 table 79. dma_adc control register (dmaactl) . . . . . . . . . . 130 table 80. dma_adc status register (dmaa_stat) . . . . . . . . . 131 table 81. adc control register (adcctl) . . . . . . . . . . . . . . . . . 135 table 82. adc data high byte register (adcd_h) . . . . . . . . . . . 137 table 83. adc data low bits register (adcd_l) . . . . . . . . . . . . 137 table 84. z8f640x family flash memory configurations . . . . . . . 138 table 85. flash code protection using the option bits . . . . . . . . . 142 table 86. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . 144 table 87. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . 145 table 88. flash page select register (fps) . . . . . . . . . . . . . . . . . . . 146 table 89. flash frequency high byte register (ffreqh) . . . . . . 147 table 90. flash frequency low byte register (ffreql) . . . . . . . 147 table 91. option bits at program memory address 0000h . . . . . 149 table 92. options bits at program memory address 0001h . . . . . 150 table 93. ocd baud-rate limits . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 94. on-chip debugger commands . . . . . . . . . . . . . . . . . . . . 156 table 95. ocd control register (ocdctl) . . . . . . . . . . . . . . . . . 161 table 96. ocd status register (ocdstat) . . . . . . . . . . . . . . . . . 162 table 97. ocd watchpoint control/add ress (wptctl) . . . . . . . 163 table 98. ocd watchpoint address (wptaddr) . . . . . . . . . . . . 164 table 99. ocd watchpoint data (wptdata) . . . . . . . . . . . . . . . 164 table 100. recommended crystal oscillator specifications (20mhz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
ps017611-0406 list of tables z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xiii table 101. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 167 table 102. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 103. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 104. power-on reset and voltage brown-out electrical characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . 173 table 105. flash memory electrical characteristics and timing . . . 173 table 106. watch-dog timer electrical characteristics and timing 174 table 107. analog-to-digital conv erter electrical characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 108. gpio port input timing . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 109. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . 177 table 110. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . 178 table 111. spi master mode timing . . . . . . . . . . . . . . . . . . . . . . . . 179 table 112. spi slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 113. i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 114. assembly language syntax ex ample 1 . . . . . . . . . . . . . 183 table 115. assembly language syntax ex ample 2 . . . . . . . . . . . . . 183 table 116. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 117. additional symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 118. condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 119. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 120. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . 188 table 121. block transfer instructions . . . . . . . . . . . . . . . . . . . . . . . 188 table 122. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 123. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 124. logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 125. program control instructions . . . . . . . . . . . . . . . . . . . . . . 190 table 126. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . 191 table 127. ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . 191 table 128. opcode map abbreviations . . . . . . . . . . . . . . . . . . . . . . . 203 table 129. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
ps017611-0406 manual objectives z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xvi manual objectives this product specification provides detailed operating in formation for the z8f640x, z8f480x, z8f320x, z8f240x, and z8f1 60x devices within the z8 encore! tm microcon- troller (mcu) family of products. within this document, the z8f640x, z8f480x, z8f320x, z8f240x, and z8f160x are referred to collectively as z8 encore! tm or the z8f640x family unless spec ifically stated otherwise. about this manual zilog recommends that the user read and un derstand everything in this manual before setting up and using the product. however, we recognize that there are different styles of learning. therefore, we have designed this pr oduct specification to be used either as a how to procedural manual or a refe rence guide to important data. intended audience this document is written for zilog custom ers who are experience d at working with microcontrollers, integrated circu its, or printed circuit assemblies. manual conventions the following assumptions and conventions are adopted to provide clarity and ease of use: courier typeface commands, code lines and fragments, bits, eq uations, hexadecimal addresses, and various executable items are distinguished from general text by the use of the courier typeface. where the use of the font is not indicated, as in the index, the name of the entity is pre- sented in upper case. ? example: flags[1] is smrf . hexadecimal values hexadecimal values are de signated by uppercase h suffix and appear in the courier typeface. ? example: r1 is set to f8h. brackets the square brackets, [ ], indicate a register or bus. ? example: for the register r1[7:0], r1 is an 8-bit register, r1[7] is the most significant bit, and r1[0] is the least significant bit.
ps017611-0406 manual objectives z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xvii braces the curly braces, { }, indicate a single register or bus created by concatenating some com- bination of smaller registers, buses, or individual bits. ? example: the 12-bit register address { 0h , rp[7:4], r1[3:0]} is composed of a 4-bit hexadecimal value ( 0h ) and two 4-bit register values taken from the register pointer (rp) and working register r1. 0h is the most significant ni bble (4-bit value) of the 12-bit register, and r1[3:0] is the least significant nibble of the 12-bit register. parentheses the parentheses, ( ), indicate an indirect register address lookup. ? example: (r1) is the memory location referenced by th e address contained in the working register r1. parentheses/bracket combinations the parentheses, ( ), indicate an indirect regi ster address lookup and the square brackets, [ ], indicate a register or bus. ? example: assume pc[15:0] contains the value 1234h . (pc[15:0]) then refers to the contents of the memory location at address 1234h . use of the words set , reset and clear the word set implies that a register bit or a cond ition contains a logical 1. the words re set or clear imply that a register bit or a condition co ntains a logical 0. when either of these terms is followed by a number, the word logical may not be included; however, it is implied. notation for bits and similar registers a field of bits within a register is designated as: register[ n : n ]. ? example: addr[15:0] refers to bits 15 through bit 0 of the address. use of the terms lsb , msb , lsb , and msb in this document, the terms lsb and msb, when appearing in upper case, mean least sig- nificant byte and most significant byte , respectively. the lowercase forms, lsb and msb , mean least significant bit and most significant bit , respectively. use of initial uppercase letters initial uppercase letters desi gnate settings, modes, and co nditions in general text. ? example 1: stop mode. ? example 2: the receiver fo rces the scl line to low. ? the master can generate a stop condition to abort the transfer.
ps017611-0406 manual objectives z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? xviii use of all uppercase letters the use of all uppercase letters designates the names of states and commands. ? example 1: the bus is considered busy after the start condition. ? example 2: a start command triggers the processing of the initialization sequence. bit numbering bits are numbered from 0 to n?1 where n indicates the total number of bits. for example, the 8 bits of a register are numbered from 0 to 7. safeguards it is important that all users understand the following safety terms, which are defined here. indicates a procedure or file may become corrupted if the user does not fol- low directions. trademarks zilog, ez8, z8 encore!, and z8 are trademarks of zilog, inc. in the u.s.a. and other countries. all other trademarks are the pr operty of their respective corporations. caution:
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 introduction 1 introduction the z8 encore! ? mcu family of products are the firs t in a line of zilog microcontroller products based upon the new 8-bit ez8 cpu. the z8f640x/z8f480x/z8f320x/z8f240x/ z8f160x products are referred to co llectively as either z8 encore! ? or the z8f640x fam- ily. the z8f640x family of pr oducts introduce flash memory to zilog?s extensive line of 8-bit microcontrollers. th e flash in-circuit programming capability allows for faster development time and program changes in the field. the new ez8 cpu is upward compat- ible with existing z8 instructions. the rich peripheral set of the z8f640x family makes it suitable for a variety of applications includ ing motor control, secu rity systems, home appliances, personal electronic devices, and sensors. features ? ez8 cpu, 20 mhz operation ? 12-channel, 10-bit analog-to-digital converter (adc) ? 3-channel dma ? up to 64kb flash memory with in-circuit programming capability ? up to 4kb register ram ? serial communication protocols ? serial peripheral interface ?i 2 c ? two full-duplex 9-bit uarts ? 24 interrupts with programmable priority ? three or four 16-bit timers with capture, compare, and pwm capability ? single-pin on-chip debugger ? two infrared data association (irda)-c ompliant infrared encoder/decoder s integrated with the uarts ? watch-dog timer (wdt) with internal rc oscillator ? up to 60 i/o pins ? voltage brown-out protection (vbo)
ps017611-0406 introduction z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 2 ? power-on reset (por) ? 3.0-3.6v operating voltage with 5v-tolerant inputs ? 0 to +70c standard temperature and -40 to +105c extended temperature operating ranges part selection guide table 1 identifies the basic features and pack age styles available for each device within the z8f640x family product line. table 1. z8f640x family part selection guide part number flash (kb) ram (kb) i/o 16-bit timers with pwm adc inputs uarts with irda i 2 cspi 40/44-pin packages 64/68-pin packages 80-pin package z8f1601 16 2 31 3 8 2 1 1 x z8f1602 16 2 46 4 12 2 1 1 x z8f2401 24 2 31 3 8 2 1 1 x z8f2402 24 2 46 4 12 2 1 1 x z8f3201 32 2 31 3 8 2 1 1 x z8f3202 32 2 46 4 12 2 1 1 x z8f4801 48 4 31 3 8 2 1 1 x z8f4802 48 4 46 4 12 2 1 1 x z8f4803 48 4 60 4 12 2 1 1 x z8f6401 64 4 31 3 8 2 1 1 x z8f6402 64 4 46 4 12 2 1 1 x z8f6403 64 4 60 4 12 2 1 1 x
ps017611-0406 introduction z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 3 block diagram figure 55 illustrates the block diagram of the architecture of the z8 encore! tm. figure 55. z8 encore! ? block diagram cpu and peripheral overview ez8 cpu features the ez8, zilog?s latest 8-bit central pro cessing unit (cpu), meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cpu executes a superset of the original z8 instruction set. the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and d ecreasing the required program memory gpio irda uarts i 2 c timers spi adc flash flash controller ram ram controller memory interrupt controller on-chip debugger ez8 cpu wdt with rc oscillator por/vbo & reset controller xtal / rc oscillator register bus memory busses system clock dma
ps017611-0406 introduction z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 4 ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks ? compatible with existing z8 code ? expanded internal register file allows access of up to 4kb ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c-compiler friendly ? 2-9 clock cycles per instruction for more information regardin g the ez8 cpu, refer to the ez8 cpu user manual avail- able for download at www.zilog.com . general purpose i/o the z8 encore! ? features seven 8-bit ports (ports a- g) and one 4-bit port (port h) for general purpose i/o (gpio). each pin is individually programmable. flash controller the flash controller programs and erases the flash memory. 10-bit analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from up to 12 different analog input sources. uarts each uart is full-duplex and capable of handling asynchronous data transfers. the uarts support 8- and 9-bit data modes and selectable parity. i 2 c the inter-integrated circuit (i 2 c ? ) controller makes the z8 encore! ? compatible with the i 2 c protocol. the i 2 c controller consists of two bidirec tional bus lines, a serial data (sda) line and a serial cl ock (scl) line.
ps017611-0406 introduction z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 5 serial peripheral interface the serial peripheral interface (spi) allows the z8 encore! ? to exchange data between other peripheral devices such as eeproms, a/ d converters and isdn devices. the spi is a full-duplex, synchronous, character-oriented ch annel that supports a four-wire interface. timers up to four 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provide a 16 -bit programmable reload counter and oper- ate in one-shot, continuous, gated, captur e, compare, capture and compare, and pwm modes. only 3 timers (timers 0-2) are av ailable in the 40- and 44-pin packages. interrupt controller the z8f640x family products support up to 24 interrupts. these interrupts consist of 12 internal and 12 general-purpose i/o pins. th e interrupts have 3 leve ls of programmable interrupt priority. reset controller the z8f640x family can be reset using the reset pin, power-on reset, watch-dog timer (wdt), stop mode exit, or voltage brown-out (vbo) warning signal. on-chip debugger the z8 encore! ? features an integrated on-chip debugger (ocd). the ocd provides a rich set of debugging capabilities, such as r eading and writing registers, programming the flash, setting breakpoints and executing code. a single-pin interface provides communi- cation to the ocd. dma controller the z8f640x family features three channels of dma. two of the channels are for register ram to and from i/o operations. the third chan nel automatically controls the transfer of data from the adc to the memory.
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 signal and pin descriptions 6 signal and pin descriptions overview the z8f640x family products ar e available in a variety of p ackages styles and pin config- urations. this chapter describes the signals an d available pin configur ations for each of the package styles. for informatio n regarding the physical pack age specifications, please refer to the chapter pack aging on page 206. available packages table 2 identifies the package styles that ar e available for each device within the z8f640x family product line. table 2. z8f640x family package options part number 40-pin pdip 44-pin lqfp 44-pin plcc 64-pin lqfp 68-pin plcc 80-pin qfp z8f1601 x x x z8f1602 x x z8f2401 x x x z8f2402 x x z8f3201 x x x z8f3202 x x z8f4801 x x x z8f4802 x x z8f4803 x z8f6401 x x x z8f6402 x x z8f6403 x
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 7 pin configurations figures 56 through 61 illustrate the pin configurations for all of the packages available in the z8 encore! ? mcu family. refer to table 2 for a description of the signals. figure 56. z8fxx01 in 40-pin dual inline package (dip) pd5 / txd1 pc4 / mosi pa4 / rxd0 pa5 / txd0 pa6 / scl pa7 / sda pd6 / cts1 pc3 / sck vss pd4/rxd1 pd3 pc5 / miso pa3 / cts0 pa2 pa1 / t0out pa0 / t0in pc2 / ss 140 vdd reset pc6 / t2in * dbg pc1 / t1out vss pd1 pd0 pc0 / t1in xout avss xin vref avdd pb2 / ana2 pb3 / ana3 pb7 / ana7 pb0 / ana0 pb1 / ana1 pb4 / ana4 20 21 pb6 / ana6 pb5 / ana5 5 10 15 35 30 25 vdd * t2out is not supported. note: timer 3 is not supported.
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 8 figure 57. z8fxx01 in 44-pin pl astic leaded chip carrier (plcc) pa7 / sda pd6 / cts1 pc3 / sck vss vdd vss pc7 / t2out pc6 / t2in dbg pa0 / t0in pd2 pc2 / ss reset vdd vss vdd pd1 pd0 7 39 pc1 / t1out xout pc0 / t1in xin pa1 / t0out pa2 pa3 / cts0 pc5 / miso pd3 pd4 / rxd1 pd5 / txd1 pc4 / mosi pa4 / rxd0 pa5 / txd0 pa6 / scl avdd pb6 / ana6 pb5 / ana5 pb0 / ana0 pb1 / ana1 pb4 / ana4 pb7 / ana7 vref pb2 / ana2 pb3 / ana3 avss 640 1 17 29 28 18 12 23 34 note: timer 3 is not supported.
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 9 figure 58. z8fxx01 in 44-pin low- profile quad flat package (lqfp) pa7 / sda pd6 / cts1 pc3 / sck vss vdd vss pc7 / t2out pc6 / t2in dbg pa0 / t0in pd2 pc2 / ss reset vdd vss vdd pd1 pd0 34 22 pc1 / t1out xout pc0 / t1in xin pa1 / t0out pa2 pa3 / cts0 pc5 / miso pd3 pd4 / rxd1 pd5 / txd1 pc4 / mosi pa4 / rxd0 pa5 / txd0 pa6 / scl avdd pb6 / ana6 pb5 / ana5 pb0 / ana0 pb1 / ana1 pb4 / ana4 pb7 / ana7 vref pb2 / ana2 pb3 / ana3 avss 33 23 44 12 11 1 28 39 17 6 note: timer 3 is not supported.
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 10 figure 59. z8fxx02 in 64-pin low- profile quad flat package (lqfp) pa7 / sda pd6 / cts1 pc3 / sck pd7 / rcout vss pe5 pe6 pe7 vdd pa0 / t0in pd2 pc2 / ss reset vdd pe4 pe3 vss pe2 49 32 pg3 pe1 vdd pe0 pa1 / t0out pa2 pa3 / cts0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 pb0 / ana0 avdd ph0 / ana8 ph1 / ana9 pb4 / ana4 pb7 / ana7 pb6 / ana6 pb5 / ana5 pb3 / ana3 48 1 pc7 / t2out pc6 / t2in dbg pc1 / t1out pc0 / t1in 17 pb2 / ana2 vref ph3 / ana11 ph2 / ana10 avss 16 vss pd1 / t3out pd0 / t3in xout xin 64 pd3 vdd pa4 / rxd0 pa5 / txd0 pa6 / scl 33 vss 56 40 25 8
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 11 figure 60. z8fxx02 in 68-pin pl astic leaded chip carrier (plcc) pa7 / sda pd6 / cts1 pc3 / sck pd7 / rcout vss pe5 pe6 pe7 vdd pa0 / t0in pd2 pc2 / ss reset vdd pe4 pe3 vss pe2 10 60 pg3 pe1 vdd pe0 pa1 / t0out pa2 pa3 / cts0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4 / mosi vss pb1 / ana1 pb0 / ana0 avdd ph0 / ana8 pb4 / ana4 pb7 / ana7 pb6 / ana6 pb5 / ana5 pb3 / ana3 9 27 pc7 / t2out pc6 / t2in dbg pc1 / t1out pc0 / t1in pb2 / ana2 vref ph3 / ana11 ph2 / ana10 avss vss vdd pd1 / t3out pd0 / t3in xout pd3 vss pa4 / rxd0 pa5 / txd0 vdd ph1 / ana9 pa6 / scl 61 vss 44 avss 43 xin 26 1 vdd 18 35 52
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 12 figure 61. z8fxx03 in 80-pin quad flat package (qfp) pa7 / sda pd6 / cts1 pc3 / sck pd7 / rcout pg0 vss pg1 pg2 pe5 pa0 / t0in pd2 pc2 / ss pf6 reset vdd pf5 pf4 pf3 1 64 pe6 pe4 pe7 pe3 pa1 / t0out pa2 pa3 / cts0 vss vdd pf7 pc5 / miso pd4 / rxd1 pd5 / txd1 pc4/mosi vss pb1 / ana1 pb0 / ana0 avdd ph0 / ana8 pb4 / ana4 pb7 / ana7 pb6 / ana6 pb5 / ana5 pb3 / ana3 80 25 vdd pg3 pg4 pg5 pg6 pb2 / ana2 vref ph3 / ana11 ph2 / ana10 avss vss pe2 pe1 pe0 vss pd3 vdd pa4 / rxd0 pa5 / txd0 pa6 / scl vss ph1 / ana9 65 vdd 40 pf2 pg7 pf1 pc7 / t2out pc6 / t2in dbg pc1 / t1out pc0 / t1in pf0 vdd pd1 / t3out pd0 / t3in xout vss 41 xin 24 5 10 15 20 30 35 45 50 55 60 70 75
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 13 signal descriptions table 2 describes the z8f640x family signals. refer to the section pin configurations on page 7 to determine the signals availabl e for the specific package styles. table 2. signal descriptions signal mnemonic i/o description general-purpose i/o ports a-h pa[7:0] i/o port a[7:0]. these pins are used for general-purpose i/o. pb[7:0] i/o port b[7:0]. these pins are used for general-purpose i/o. pc[7:0] i/o port c[7:0]. these pins are used for general-purpose i/o. pd[7:0] i/o port d[7:0]. these pins are used for general-purpose i/o. pe[7:0] i/o port e[7:0]. these pins are used for general-purpose i/o. pf[7:0] i/o port f[7:0]. these pins are used for general-purpose i/o. pg[7:0] i/o port g[7:0]. these pins are used for general-purpose i/o. ph[3:0] i/o port h[3:0]. these pins are used for general-purpose i/o. i 2 c controller scl o serial clock. this is the output clock for the i 2 c. this pin is multiplexed with a general-purpose i/o pin. when the gene ral-purpose i/o pin is configured for alternate function to enable the scl function, this pin is open-drain. sda i/o serial data. this open -drain pin is used to tr ansfer data between the i 2 c and a slave. this pin is multiplexed with a general-purpose i/o pin. when the general- purpose i/o pin is configured for alternate function to enable the sda function, this pin is open-drain. spi controller ss i/o slave select. this signal can be an output or an input. if the z8 encore! is the spi master, this pin may be configured as the slave select output. if the z8 encore! is the spi slave, this pin is the input slave select. it is multiplexed with a general- purpose i/o pin. sck i/o spi serial clock. the spi master supplies this pin. if the z8 encore! is the spi master, this pin is an output. if the z8 encore! is the spi slave, this pin is an input. it is multiplexed with a general-purpose i/o pin. mosi i/o master out slave in. this signal is th e data output from the spi master device and the data input to the spi slave device. it is multiplexed with a general-purpose i/o pin. miso i/o master in slave out. this pin is the data input to the spi master device and the data output from the spi slave device. it is multiplexed with a general-purpose i/o pin.
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 14 uart controllers txd0 / txd1 o transmit data. these signals are th e transmit outputs from the uarts. the txd signals are multiplexed with general-purpose i/o pins. rxd0 / rxd1 i receive data. these signals are th e receiver inputs for the uarts and irdas. the rxd signals are multiplexed with general-purpose i/o pins. cts0 / cts1 i clear to send. these signals are co ntrol inputs for the uarts. the cts signals are multiplexed with general-purpose i/o pins. timers (timer 3 is un available in the 40-and 44-pin packages) t0out / t1out/ t2out / t3out o timer output 0-3. these signals are output pins from the timers. the timer output signals are multiplexed with general-purpose i/o pins. t2out is not supported in the 40-pin package. t3out is not supported in the 40- and 44-pin packages. t0in / t1in/ t2in / t3in i timer input 0-3. these signals are used as the capture, gating and counter inputs. the timer input signals are multiplexed with general-purpose i/o pins. t3in is not supported in the 40- and 44-pin packages. analog ana[11:0] i analog input. these signals are inputs to the anal og-to-digital converter (adc). the adc analog inputs are multiplexed with general-purpose i/o pins. vref i analog-to-digital converter reference voltage input. the vref pin should be left unconnected (or capacitively coupled to analog ground) if the internal voltage reference is selected as the adc reference voltage. oscillators xin i external crystal input. this is the input pin to the crystal oscillator. a crystal can be connected betw een it and the xout pin to form the oscillator. xout o external crystal output. this pin is the output of the crystal oscillator. a crystal can be connected between it and the xin pin to form the oscillator. when the system clock is referred to in this manual, it refers to the freque ncy of the signal at this pin. rcout o rc oscillator output. this signal is the output of the rc oscillator. it is multiplexed with a general-purpose i/o pin. on-chip debugger dbg i/o debug. this pin is the control and data input and output to and from the on-chip debugger. for operation of the on-chip debugger, all power pins (v dd and av dd must be supplied with power, and all ground pins (v ss and av ss must be grounded. this pin is open-drain and must have an external pull-up resistor to ensure proper operation. table 2. signal descriptions (continued) signal mnemonic i/o description
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 15 pin characteristics table 3 provides detailed info rmation on the characteristics for each pin available on the z8f640x family products. data in table 3 is sorted alphabetically by the pin symbol mne- monic. reset reset i reset. generates a reset when asserted (driven low). power supply vdd i power supply. avdd i analog power supply. vss i ground. avss i analog ground. table 3. pin characteristics of the z8f640x family symbol mnemonic direction reset direction active low or active high tri-state output internal pull-up or pull-down schmitt trigger input open drain output avss n/a n/a n/a n/a no no n/a avdd n/a n/a n/a n/a no no n/a db g i/ o i n /a yes no yes yes vss n/a n/a n/a n/a no no n/a pa[7:0] i/o i n/a yes no yes yes, programmable pb[7:0] i/o i n/a yes no yes yes, programmable pc[7:0] i/o i n/a yes no yes yes, programmable pd[7:0] i/o i n/a yes no yes yes, programmable pe7:0] i/o i n/a yes no yes yes, programmable x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer table 2. signal descriptions (continued) signal mnemonic i/o description
ps017611-0406 signal and pin descriptions z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 16 pf[7:0] i/o i n/a yes no yes yes, programmable pg[7:0] i/o i n/a yes no yes yes, programmable ph[3:0] i/o i n/a yes no yes yes, programmable reset i i low n/a pull-up yes n/a vdd n/a n/a n/a n/a no no n/a xin i i n/a n/a no no n/a xout o o n/a yes, in stop mode no no no table 3. pin characteristics of the z8f640x family symbol mnemonic direction reset direction active low or active high tri-state output internal pull-up or pull-down schmitt trigger input open drain output x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 address space 17 address space overview the ez8 cpu can access three distinct address spaces: ? the register file contains addresses for the general-purpose registers and the ez8 cpu, peripheral, and general-purp ose i/o port control registers. ? the program memory contains addresses for all memory locations having executable code and/or data. ? the data memory contains addresses for all memory locations that hold data only. these three address spaces are covered brie fly in the following subsections. for more detailed information regarding the ez8 cp u and its address space, refer to the ez8 cpu user manual available for download at www.zilog.com . register file the register file address space in the z8 encore! ? is 4kb (4096 bytes). the register file is composed of two sections?control regist ers and general-purpose registers. when instructions are execut ed, registers are read from when defined as sources and written to when defined as destinations. the architecture of the ez8 cpu allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256-byte control register section are reserved (unavailable). reading from an reserved register file addresses returns an undefined value. writing to re served register file addresses is not recom- mended and can produce unpredictable results. the on-chip ram always begins at address 00 0h in the register file address space. the z8f640x family products contain 2kb to 4kb of on-chip ram depending upon the device. reading from register file addresses outside the available ram addresses (and not within in the control register address sp ace) returns an undefined value. writing to these register file addresses produces no effect. refer to the part selection guide sec- tion of the introduction chapter to determine the amount of ram available for the spe- cific z8f640x family device.
ps017611-0406 address space z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 18 program memory the ez8 cpu supports 64kb of program me mory address space. the z8f640x family devices contain 16kb to 64kb of on-chip flash memory in the program memory address space. reading from program memory addres ses outside the available flash memory addresses returns ffh . writing to these unemployments program memory addresses pro- duces no effect. table 4 describes the prog ram memory maps for the z8f640x family products. table 4. z8f640x family program memory maps program memory address (hex) function z8f160x products 0000-0001 flash option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-3fffh program memory z8f240x products 0000-0001 flash option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-5fffh program memory z8f320x products 0000-0001 flash option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-7fffh program memory * see table 22 on page 45 for a list of the interrupt vectors.
ps017611-0406 address space z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 19 data memory the z8f640x family devices contain 128 bytes of read-only memory at the top of the ez8 cpu?s 64kb data memory address space. th e ez8 cpu?s lde and ldei instructions provide access to the data memory informatio n. table 5 describes the z8f640x family?s data memory map. z8f480x products 0000-0001 flash option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-bfffh program memory z8f640x products 0000-0001 flash option bits 0002-0003 reset vector 0004-0005 wdt interrupt vector 0006-0007 illegal instruction trap 0008-0037 interrupt vectors* 0038-ffffh program memory table 5. z8f640x family data memory maps data memory address (hex) function 0000h-ffbfh reserved ffc0h-ffd3h part number 20-character ascii alphanumeric code left justified and filled with zeros ffd4h-ffffh reserved table 4. z8f640x family program memory maps (continued) program memory address (hex) function * see table 22 on page 45 for a list of the interrupt vectors.
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 register file address map 20 register file address map table 6 provides the address map for the register file of the z8f640x family of products. not all devices and package styles in the z8f6 40x family support timer 3 and all of the gpio ports. consider registers for unimplemented peripherals as reserved. table 6. register file address map address (hex) register description mnemonic reset (hex) page # general purpose ram 000-eff general-purpose register file ram ? xx timer 0 f00 timer 0 high byte t0h 00 66 f01 timer 0 low byte t0l 01 66 f02 timer 0 reload high byte t0rh ff 67 f03 timer 0 reload low byte t0rl ff 67 f04 timer 0 pwm high byte t0pwmh 00 69 f05 timer 0 pwm low byte t0pwml 00 69 f06 reserved ? xx f07 timer 0 control t0ctl 00 70 timer 1 f08 timer 1 high byte t1h 00 66 f09 timer 1 low byte t1l 01 66 f0a timer 1 reload high byte t1rh ff 67 f0b timer 1 reload low byte t1rl ff 67 f0c timer 1 pwm high byte t1pwmh 00 69 f0d timer 1 pwm low byte t1pwml 00 69 f0e reserved ? xx f0f timer 1 control t1ctl 00 70 timer 2 f10 timer 2 high byte t2h 00 66 f11 timer 2 low byte t2l 01 66 f12 timer 2 reload high byte t2rh ff 67 f13 timer 2 reload low byte t2rl ff 67 f14 timer 2 pwm high byte t2pwmh 00 69 f15 timer 2 pwm low byte t2pwml 00 69 f16 reserved ? xx f17 timer 2 control t2ctl 00 70 xx=undefined
ps017611-0406 register file address map z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 21 timer 3 (not available in 40- and 44- pin packages) f18 timer 3 high byte t3h 00 66 f19 timer 3 low byte t3l 01 66 f1a timer 3 reload high byte t3rh ff 67 f1b timer 3 reload low byte t3rl ff 67 f1c timer 3 pwm high byte t3pwmh 00 69 f1d timer 3 pwm low byte t3pwml 00 69 f1e reserved ? xx f1f timer 3 control t3ctl 00 70 f20-f3f reserved ? xx uart 0 f40 uart0 transmit data u0txd xx 86 uart0 receive data u0rxd xx 87 f41 uart0 status 0 u0stat0 0000011xb 87 f42 uart0 control 0 u0ctl0 00 89 f43 uart0 control 1 u0ctl1 00 89 f44 uart0 status 1 u0stat1 00 87 f45 reserved ? xx f46 uart0 baud rate high byte u0brh ff 91 f47 uart0 baud rate low byte u0brl ff 91 uart 1 f48 uart1 transmit data u1txd xx 86 uart1 receive data u1rxd xx 87 f49 uart1 status 0 u1stat0 0000011xb 87 f4a uart1 control 0 u1ctl0 00 89 f4b uart1 control 1 u1ctl1 00 89 f4c uart1 status 1 u1stat1 00 87 f4d reserved ? xx f4e uart1 baud rate high byte u1brh ff 91 f4f uart1 baud rate low byte u1brl ff 91 i 2 c f50 i 2 c data i2cdata 00 118 f51 i 2 c status i2cstat 80 118 f52 i 2 c control i2cctl 00 119 f53 i 2 c baud rate high byte i2cbrh ff 121 f54 i 2 c baud rate low byte i2cbrl ff 121 f55-f5f reserved ? xx serial peripheral interface (spi) f60 spi data spidata xx 106 f61 spi control spictl 00 107 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps017611-0406 register file address map z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 22 f62 spi status spistat 01 108 f63 spi mode spimode 00 109 f64-f65 reserved ? xx f66 spi baud rate high byte spibrh ff 110 f67 spi baud rate low byte spibrl ff 110 f68-f69 reserved ? xx analog-to-digital converter (adc) f70 adc control adcctl 20 135 f71 reserved ? xx f72 adc data high byte adcd_h xx 137 f73 adc data low bits adcd_l xx 137 f74-faf reserved ? xx dma 0 fb0 dma0 control dma0ctl 00 124 fb1 dma0 i/o address dma0io xx 125 fb2 dma0 end/start address high nibble dma0h xx 126 fb3 dma0 start address low byte dma0start xx 127 fb4 dma0 end address low byte dma0end xx 128 dma 1 fb8 dma1 control dma1ctl 00 124 fb9 dma1 i/o address dma1io xx 125 fba dma1 end/start address high nibble dma1h xx 126 fbb dma1 start address low byte dma1start xx 127 fbc dma1 end address low byte dma1end xx 128 dma adc fbd dma_adc address dmaa_addr xx 128 fbe dma_adc control dmaactl 00 130 fbf dma_adc status dmaastat 00 131 interrupt controller fc0 interrupt request 0 irq0 00 48 fc1 irq0 enable high bit irq0enh 00 51 fc2 irq0 enable low bit irq0enl 00 51 fc3 interrupt request 1 irq1 00 49 fc4 irq1 enable high bit irq1enh 00 52 fc5 irq1 enable low bit irq1enl 00 52 fc6 interrupt request 2 irq2 00 50 fc7 irq2 enable high bit irq2enh 00 53 fc8 irq2 enable low bit irq2enl 00 53 fc9-fcc reserved ? xx fcd interrupt edge select irqes 00 54 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps017611-0406 register file address map z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 23 fce interrupt port select irqps 00 55 fcf interrupt control irqctl 00 56 gpio port a fd0 port a address paaddr 00 37 fd1 port a control pactl 00 38 fd2 port a input data pain xx 42 fd3 port a output data paout 00 43 gpio port b fd4 port b address pbaddr 00 37 fd5 port b control pbctl 00 38 fd6 port b input data pbin xx 42 fd7 port b output data pbout 00 43 gpio port c fd8 port c address pcaddr 00 37 fd9 port c control pcctl 00 38 fda port c input data pcin xx 42 fdb port c output data pcout 00 43 gpio port d fdc port d address pdaddr 00 37 fdd port d control pdctl 00 38 fde port d input data pdin xx 42 fdf port d output data pdout 00 43 gpio port e fe0 port e address peaddr 00 37 fe1 port e control pectl 00 38 fe2 port e input data pein xx 42 fe3 port e output data peout 00 43 gpio port f fe4 port f address pfaddr 00 37 fe5 port f control pfctl 00 38 fe6 port f input data pfin xx 42 fe7 port f output data pfout 00 43 gpio port g fe8 port g address pgaddr 00 37 fe9 port g control pgctl 00 38 fea port g input data pgin xx 42 feb port g output data pgout 00 43 gpio port h fec port h address phaddr 00 37 table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps017611-0406 register file address map z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 24 fed port h control phctl 00 38 fee port h input data phin xx 42 fef port h output data phout 00 43 watch-dog timer (wdt) ff0 watch-dog timer control wdtctl xxx00000b 75 ff1 watch-dog timer reload upper byte wdtu ff 76 ff2 watch-dog timer relo ad high byte wdth ff 76 ff3 watch-dog timer relo ad low byte wdtl ff 76 ff4--ff7 reserved ? xx flash memory controller ff8 flash control fctl 00 144 ff8 flash status fstat 00 145 ff9 flash page select fps 00 146 ffa flash programming frequency high byte ffreqh 00 147 ffb flash programming frequency low byte ffreql 00 147 ez8 cpu ffc flags ? xx refer to the ez8 cpu user manual ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 6. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps017611-0406 reset and stop mode recovery z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 25 reset and stop mode recovery overview the reset controller within the z8f640x fam ily devices controls reset and stop mode recovery operation. in typical operation, the following events cause a reset to occur: ? power-on reset (por) ? voltage brown-out (vbo) ? watch-dog timer time-out (when configured via the wdt_res option bit to initiate a reset) ? external reset pin assertion ? on-chip debugger initiated reset (ocdctl[1] set to 1) when the z8f640x fa mily device is in stop mode, a stop mode r ecovery is initiated by either of the following: ? watch-dog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source ? dbg pin driven low reset types the z8f640x family provides several differen t types of reset operation. stop mode recovery is considered a form of reset. the ty pe of reset is a function of both the current operating mode of the z8f640x family device and the source of the reset. table 7 lists the types of reset and their operating characteris tics. the system reset is longer than the short reset to allow additional time for external oscillator start-up. table 7. reset and stop mode rec overy characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as applicable) reset 514 wd t oscillator cycles + 16 system clock cycles short reset reset (as applicable) reset 66 wdt oscillator cycles + 16 system clock cycles stop mode recovery unaffected, except wdt_ctl register reset 514 wdt oscillator cycl es + 16 system clock cycles
ps017611-0406 reset and stop mode recovery z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 26 system and short resets during a system reset, the z8f640 x family device is held in reset for 514 cycles of the watch-dog timer oscillator followed by 16 cycles of the system clock (crystal oscillator). a short reset differs from a system reset only in the number of watch-dog timer oscil- lator cycles required to exit reset. a short r eset requires only 66 watch-dog timer oscil- lator cycles. unless specifically stated ot herwise, system reset and short reset are referred to collectively as reset. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watch-dog timer os cillator continue to run. th e system clock begins oper- ating following the watch-dog timer oscillat or cycle count. the ez8 cpu and on-chip peripherals remain idle through th e 16 cycles of th e system clock. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other control registers (including the stack pointer, regis- ter pointer, and flags) and general-purpo se ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. prog ram execution begins at the reset vector address. reset sources table 8 lists the reset sources and type of reset as a function of the z8f640x family device operating mode. the text following prov ides more detailed information on the indi- vidual reset sources. please note that power-on reset / voltage brown-out events always have priority over all other possible reset so urces to insure a full system reset occurs. table 8. reset sources and resulting reset type operating mode reset source reset type normal or halt modes power-on reset / voltage brown-out system reset watch-dog timer time-out when configured for reset short reset reset pin assertion short reset on-chip debugger initiated reset (ocdctl[1] set to 1) system reset except the on-chip debugger is unaffected by the reset stop mode power-on reset / voltage brown-out system reset reset pin assertion system reset dbg pin driven low system reset
ps017611-0406 reset and stop mode recovery z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 27 power-on reset the z8f640x family products contain an in ternal power-on reset (por) circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the por counter is enabled and counts 514 cycles of the watch-dog timer oscillator. after the por counter times out, the xtal counter is enabled to count a total of 16 system clock pulses. the z8f640x fam ily device is held in the reset state until both the por counter an d xtal counter have timed out. after the device exits the power-on reset state, the ez8 cpu fetches the reset vector. following power-on reset, the por status bit in the watch-dog ti mer control (wdtctl) register is set to 1. figure 62 illustrates power-on reset operation. refer to the electrical characteristics chapter for the por threshold voltage (v por ). figure 62. power-on reset operation (not to scale) voltage brown-out reset the devices in the z8f640x family provid e low voltage brown-out (vbo) protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo vcc = 0.0v vcc = 3.3v v por v vbo crystal oscillator xout internal reset signal program execution oscillator start-up xtal wdt clock por counter delay counter delay
ps017611-0406 reset and stop mode recovery z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 28 threshold voltage, v vbo ) and forces the device into the r eset state. while the supply volt- age remains below the power-on reset voltage threshold (v por ), the vbo block holds the z8f640x family device in the reset state. after the supply voltage again exceeds th e power-on reset voltage threshold, the z8f640x family device progresses through a fu ll system reset sequence, as described in the power-on reset section. following power-on reset, the por status bit in the watch- dog timer control (wdtctl) register is set to 1. figure 63 illustrates voltage brown- out operation. refer to the electrical characteristics chapter for the vbo and por threshold voltages (v vbo and v por ). stop mode disables the voltage brown-out detector. figure 63. voltage brown-out reset operation (not to scale) watch-dog timer reset if the device is in normal or halt mode, th e watch-dog timer can initiate a system reset at time-out if the wdt_res option bit is set to 1. this is the default (unprogrammed) set- ting of the wdt_res option bit. the wdt status bit in the wdt co ntrol register is set to signify that the reset was initiated by the watch-dog timer. vcc = 3.3v v por v vbo internal reset signal program execution program execution voltage brownout vcc = 3.3v crystal oscillator xout wdt clock xtal por counter delay counter delay
ps017611-0406 reset and stop mode recovery z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 29 external pin reset the reset pin has a schmitt-triggered input an d an internal pull-up. once the reset pin is asserted, the device progresses thro ugh the short reset sequence. while the reset input pin is asserted low, the z8f640x family device continue s to be held in the reset state. if the reset pin is held low beyond the short reset time-out, the device exits the reset state immediately following reset pin deassertion. following a short reset initi- ated by the external reset pin, the ext status bit in the watch-dog timer control (wdtctl) register is set to 1. stop mode recovery stop mode is entered by execution of a stop instruction by the ez8 cpu. refer to the low-power modes chapter for detailed stop mode information. during stop mode recovery, the z8f640x family device is held in reset for 514 cycles of the watch-dog timer oscillator followed by 16 cycles of the system clock (crystal oscillator). stop mode recovery does not affect any values in the regi ster file, including th e stack pointer, reg- ister pointer, flags and general-purpose ram. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counte r. program execution begins at the reset vec- tor address. following stop mode recovery, the stop bit in the watch-dog timer con- trol register is set to 1. table 9 lists the stop mode recovery sources and resulting actions. the text following prov ides more detailed informatio n on each of the stop mode recovery sources. stop mode recovery using watch-dog timer time-out if the watch-dog timer times out during stop mode, the z8f640x family device under- goes a stop mode recovery sequence. in the watch-dog timer control register, the wdt and stop bits are set to 1. if the watch-do g timer is configured to generate an inter- rupt upon time-out and the device is configured to respond to interrupts, the z8f640x fam- ily device services the watch-dog timer inte rrupt request following the normal stop mode recovery sequence. table 9. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watch-dog timer time-out when configured for reset stop mode recovery watch-dog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery
ps017611-0406 reset and stop mode recovery z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 30 stop mode recovery using a gpio port pin transition each of the gpio port pins may be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recover source, a change in the input pin value (from high to low or from low to high) initia tes stop mode recovery. in the watch-dog timer control register, the stop bit is set to 1. in stop mode, the gpio po rt input data registers (p x in) are disabled. the port input data registers record the po rt transition only if the signal stays on the port pin through the end of the stop mode recovery delay. thus, short pulses on the port pin can ini tiate stop mode recovery without be- ing written to the port input data regi ster or without initiating an interrupt (if enabled for that pin). caution:
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 low-power modes 31 low-power modes overview the z8f640x family products contain power-saving features. the highest level of power reduction is provided by stop mode. the next level of power reductio n is provided by the halt mode. stop mode execution of the ez8 cpu?s stop instruction places the z8f640x family device into stop mode. in stop mode, the operating characteristics are: ? primary crystal oscillator is stopped ? system clock is stopped ? ez8 cpu is stopped ? program counter (pc) stops incrementing ? watch-dog timer?s internal rc oscillator continues to operate ? if enabled, the watch-dog ti mer continues to operate ? all other on-chip peripherals are idle to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). the z8f640x family device can be brought out of stop mode using stop mode recovery. for more information on stop mode recovery refer to the reset and stop mode recovery chapter. halt mode execution of the ez8 cpu?s halt instruction pl aces the z8f640x family device into halt mode. in halt mode, the oper ating characteristics are: ? primary crystal oscillator is en abled and continues to operate ? system clock is enabled and continues to operate ? ez8 cpu is idle ? program counter (pc) stops incrementing
ps017611-0406 low-power modes z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 32 ? watch-dog timer?s internal rc oscillator continues to operate ? if enabled, the watch-dog ti mer continues to operate ? all other on-chip peripherals continue to operate the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watch-dog timer time-out (interrupt or reset) ? power-on reset ? voltage-brown out reset ? external reset pin assertion to minimize current in halt mode, all gpio pi ns which are configured as inputs must be driven to one of the supply rails (v cc or gnd).
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 general-purpose i/o 33 general-purpose i/o overview the z8f640x family products support a maximum of seven 8-bit ports (ports a-g) and one 4-bit port (port h) for ge neral-purpose input/output (i/o) operations. each port con- tains control and data registers. the gpio co ntrol registers are used to determine data direction, open-drain, output drive current and alternate pin functions. each port pin is individually programmable. gpio port availability by device not all z8f640x family products support all 8 ports (a-h). table 10 lists the port pins available with each device and package type. table 10. port availability by device and package type device packages port a port b port c port d port e port f port g port h z8f160140-pin [7:0][7:0][6:0][6:3, 1:0]---- z8f1601 44-pin [7:0] [7:0] [7:0] [6:0] z8f1602 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8f240140-pin [7:0][7:0][6:0][6:3, 1:0]---- z8f240144-pin [7:0][7:0][7:0][6:0]---- z8f2402 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8f320140-pin [7:0][7:0][6:0][6:3, 1:0]---- z8f320144-pin [7:0][7:0][7:0][6:0]---- z8f3202 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8f480140-pin [7:0][7:0][6:0][6:3, 1:0]---- z8f480144-pin [7:0][7:0][7:0][6:0]---- z8f4802 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8f4803 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] z8f640140-pin [7:0][7:0][6:0][6:3, 1:0]----
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 34 architecture figure 64 illustrates a simplified block diagram of a gpio port pin. in this figure, the abil- ity to accommodate alternate functions and va riable port current drive strength are not illustrated. figure 64. gpio port pin block diagram gpio alternate functions many of the gpio port pins can be used as bo th general-purpose i/o and to provide access to on-chip peripheral functions such as th e timers and serial communication devices. the port a-h alternate function sub-registers conf igure these pins for either general-purpose i/o or alternate function operation. when a pin is configured for alte rnate function, control z8f640144-pin [7:0][7:0][7:0][6:0]---- z8f6402 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0] z8f6403 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0] table 10. port availability by device and package type (continued) device packages port a port b port c port d port e port f port g port h d q dq d q gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt trigger
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 35 of the port pin direction (input/output) is passed from the port a-h data direction regis- ters to the alternate function assi gned to this pin. table 11 lists the alternate functions asso- ciated with each port pin. table 11. port alternat e function mapping port pin mnemonic alternate function description port a pa0 t0in timer 0 input pa1 t0out timer 0 output pa2 n/a no alternate function pa3 cts0 uart 0 clear to send pa4 rxd0 / irrx0 uart 0 / irda 0 receive data pa5 txd0 / irtx0 uart 0 / irda 0 transmit data pa6 scl i 2 c clock (automatically open-drain) pa7 sda i 2 c data (automatically open-drain) port b pb0 ana0 adc analog input 0 pb1 ana1 adc analog input 1 pb2 ana2 adc analog input 2 pb3 ana3 adc analog input 3 pb4 ana4 adc analog input 4 pb5 ana5 adc analog input 5 pb6 ana6 adc analog input 6 pb7 ana7 adc analog input 7 port c pc0 t1in timer 1 input pc1 t1out timer 1 output pc2 ss spi slave select pc3 sck spi serial clock pc4 mosi spi master out slave in pc5 miso spi master in slave out pc6 t2in timer 2 in pc7 t2out timer 2 out (not avai lable in 40-pin packages)
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 36 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins may be con- figured to generate an interrupt request on eith er the rising edge or falling edge of the pin input signal. other port pin interrupts generate an interrupt when any edge occurs (both rising and falling). refer to the interrupt controller chapter for more information on interrupts using the gpio pins. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 12 lists these port registers. use the po rt a-h address and control registers together to provide access to sub-registers fo r port configuration and control. port d pd0 t3in timer 3 in (not availabl e in 40- and 44-pin packages) pd1 t3out timer 3 out (not availabl e in 40- and 44-pin packages) pd2 n/a no alternate function pd3 n/a no alternate function pd4 rxd1 / irrx1 uart 1 / irda 1 receive data pd5 txd1 / irtx1 uart 1 / irda 1 transmit data pd6 cts1 uart 1 clear to send pd7 rcout watch-dog timer rc oscillator output port e pe[7:0] n/a no alternate functions port f pf[7:0] n/a no alternate functions port g pg[7:0] n/a no alternate functions port h ph0 ana8 adc analog input 8 ph1 ana9 adc analog input 9 ph2 ana10 adc analog input 10 ph3 ana11 adc analog input 11 table 11. port alternate func tion mapping (continued) port pin mnemonic alternate function description
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 37 port a-h address registers the port a-h address registers select the gp io port functionality accessible through the port a-h control registers. the port a-h ad dress and control regi sters combine to pro- vide access to all gpio port control (table 13). table 12. gpio port registers and sub-registers port register mnemonic port register name p x addr port a-h address register (selects sub-registers) p x ctl port a-h control register (provides access to sub-registers) p x in port a-h input data register p x out port a-h output data register port sub-register mnemonic port register name p x dd data direction p x af alternate function p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recovery source enable table 13. port a-h gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/w addr fd0h, fd4h, fd8h, fdch, fe0h, fe4h, fe8h, fech
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 38 paddr[7:0]?port address the port address selects one of the sub-regi sters accessible through the port control reg- ister. port a-h control registers the port a-h control registers set the gpio port operation. the va lue in the correspond- ing port a-h address register determines th e control sub-registers accessible using the port a-h control register (table 14). pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. paddr[7:0] port control sub-register accessi ble using the port a-h control registers 00h no function. provides so me protection against accident al port reco nfiguration. 01h data direction 02h alternate function 03h output control (open-drain) 04h high drive enable 05h stop mode recovery source enable. 06h-ffh no function. table 14. port a-h control registers (p x ctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/w addr fd1h, fd5h, fd9h, fddh, fe1h, fe5h, fe9h, fedh
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 39 port a-h data direction sub-registers the port a-h data direction sub-register is accessed through the port a-h control regis- ter by writing 01h to the port a-h address register (table 15). dd[7:0]?data direction these bits control the direction of the associa ted port pin. port alternate function opera- tion overrides the data direction register setting. 0 = output. data in the port a-h output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and the va lue written into the po rt a-h input data reg- ister. the output driver is tri-stated. port a-h alternate function sub-registers the port a-h alternate function sub-register (table 16) is accessed through the port a-h control register by writing 02h to the port a-h address register. the port a-h alternate function sub-registers select the alternate fu nctions for the selected pins. refer to the gpio alternate functions section to determine the alte rnate function associated with each port pin. do not enable alternate function for gp io port pins which do not have an associated alternate functi on. failure to follow this guideline may result in unpredictable operation. table 15. port a-h data direction sub-registers bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 01h in port a-h address register, accessible via port a-h control register table 16. port a-h alternat e function sub-registers bits 7 6 5 4 3 2 1 0 field af7af6af5af4af3af2af1af0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 02h in port a-h address register, accessible via port a-h control register caution:
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 40 af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a-h data direction sub- register determines the direction of the pin. 1 = the alternate function is se lected. port pin operation is controlled by the alternate function. port a-h output control sub-registers the port a-h output control sub-register (table 17) is accessed through the port a-h control register by writing 03h to the port a-h address register. setting the bits in the port a-h output control sub-registers to 1 co nfigures the specified port pins for open- drain operation. these sub-registers affect the pi ns directly and, as a result, alternate func- tions are also affected. poc[7:0]?port output control these bits function independently of the alternate function bit and disables the drains if set to 1. 0 = the drains are enabled for any output mode. 1 = the drain of the associated pin is disabled (open-drain mode). table 17. port a-h output control sub-registers bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 03h in port a-h address register, accessible via port a-h control register
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 41 port a-h high drive enable sub-registers the port a-h high drive enable sub-register (table 18) is accessed through the port a-h control register by writing 04h to the port a-h address register. setting the bits in the port a-h high drive enable sub-registers to 1 configures the specified port pins for high current output drive operation. the port a-h high drive enable sub-register affects the pins directly and, as a result, a lternate functions are also affected. phde[7:0]?port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a-h stop mode recovery source enable sub-registers the port a-h stop mode recovery source enable sub-register (table 19) is accessed through the port a-h control register by writing 05h to the port a-h address register. setting the bits in the port a-h stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. table 18. port a-h high dr ive enable sub-registers bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 04h in port a-h address register, accessible via port a-h control register
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 42 psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mo de recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. port a-h input data registers reading from the port a-h input data regist ers (table 20) returns the sampled values from the corresponding port pi ns. the port a-h input data registers are read-only. pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). table 19. port a-h stop mode rec overy source enable sub-registers bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr if 05h in port a-h address register, accessible via port a-h control register table 20. port a-h input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr addr fd2h, fd6h, fdah, fdeh, fe2h, fe6h, feah, feeh
ps017611-0406 general-purpose i/o z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 43 port a-h output data register the port a-h output data register (tab le 21) writes output data to the pins. pout[7:0]?port output data these bits contain the data to be driven ou t from the port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alter- nate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is not driven if the drain has been disabled by set- ting the corresponding port outp ut control register bit to 1. table 21. port a-h output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fd3h, fd7h, fdbh, fdfh, fe3h, fe7h, febh, fefh
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 interrupt controller 44 interrupt controller overview the interrupt controller on th e z8f640x family device prior itizes the interrupt requests from the on-chip peripherals and the gpio port pins. the features of the interrupt control- ler on the z8f640x family device include the following: ? 24 unique interrupt vectors: ? 12 gpio port pin interrupt sources ? 12 on-chip peripheral interrupt sources ? flexible gpio interrupts ? 8 selectable rising and falling edge gpio interrupts ? 4 dual-edge interrupts ? 3 levels of individually pr ogrammable interrupt priority ? watch-dog timer can be configured to generate an interrupt interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the cpu and the interrupting pe ripheral. when the service routine is com- pleted, the cpu returns to the operation from wh ich it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt control has no effe ct on operation. refer to the ez8 cpu user manual for more information regarding interrupt servicing by the ez8 cpu. the ez8 cpu user man- ual is available for download at www.zilog.com . interrupt vector listing table 22 lists all of the interrupts available on the z8f640x family device in order of pri- ority. the interrupt vector is stored with the most significant byte (msb) at the even pro- gram memory address and the least significan t byte (lsb) at the following odd program memory address.
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 45 table 22. interrupt vectors in order of priority priority program memory vector address interrupt sour ce interrupt assertion type highest 0002h reset (not an interrupt) not applicable 0004h watch-dog timer continuous assertion 0006h illegal instruction trap (not an interrupt) not applicable 0008h timer 2 single assertion (pulse) 000ah timer 1 single assertion (pulse) 000ch timer 0 single assertion (pulse) 000eh uart 0 receiver continuous assertion 0010h uart 0 transmitter continuous assertion 0012h i 2 c continuous assertion 0014h spi continuous assertion 0016h adc single assertion (pulse) 0018h port a7 or port d7, rising or falling input edge single assertion (pulse) 001ah port a6 or port d6, rising or falling input edge single assertion (pulse) 001ch port a5 or port d5, rising or falling input edge single assertion (pulse) 001eh port a4 or port d4, rising or fa lling input edge single assertion (pulse) 0020h port a3 or port d3, rising or falling input edge single assertion (pulse) 0022h port a2 or port d2, rising or falling input edge single assertion (pulse) 0024h port a1 or port d1, rising or falling input edge single assertion (pulse) 0026h port a0 or port d0, rising or falling input edge single assertion (pulse) 0028h timer 3 (not available in 40/44-pin packages) single assertion (pulse) 002ah uart 1 receiver continuous assertion 002ch uart 1 transmitter continuous assertion 002eh dma single assertion (pulse) 0030h port c3, both input edges single assertion (pulse) 0032h port c2, both input edges single assertion (pulse) 0034h port c1, both input edges single assertion (pulse) lowest 0036h port c0, both input edges single assertion (pulse)
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 46 architecture figure 65 illustrates a block diag ram of the interrupt controller. figure 65. interrupt co ntroller block diagram operation master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an ei (enable interrupt) instruction ? execution of an iret (retur n from interrupt) instruction ? writing a 1 to the irqe bit in the interrupt control register interrupts are globally disabled by any of the following actions: ? execution of a di (disable interrupt) instruction ? ez8 cpu acknowledgement of an interru pt service request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 47 ? execution of a trap instruction ? illegal instruction trap interrupt vectors and priority the z8f640x family device interrupt controller su pports three levels of interrupt priority. level 3 is the highest priority, level 2 is th e second highest priority, and level 1 is the lowest priority. if all of the interrupts were en abled with identical in terrupt priority (all as level 2 interrupts, for example) , then interrupt priority woul d be assigned from highest to lowest as specified in table 22. level 3 interrupt s always have higher priority than level 2 interrupts which, in turn, always have higher priority than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is ass igned as specified in table 22. reset, watch-dog timer interrupt (if enabled) , and illegal instruction trap always have highest (level 3) priority. interrupt assertion types two types of interrupt assertion - single a ssertion (pulse) and continuous assertion - are used within the z8f640x family device. the type of interrupt assert ion for each interrupt source is listed in table 22. single assertion (pulse) interrupt sources some interrupt sources assert their interrupt re quests for only a single system clock period (single pulse). when the interrupt request is acknowledged by the ez8 cpu, the corre- sponding bit in the interrupt request register is cleared un til the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt request re gister likewise clears the interrupt request. continuous assertion interrupt sources other interrupt sources contin uously assert their interrupt requests until cleared at the source. for these continuous assertion interru pt sources, interrupt acknowledgement by the ez8 cpu does not clear the corresponding bi t in the interrupt re quest register. writing a 0 to the corresponding bit in the interrupt re quest register only clears the interrupt for a single clock cycle. since the source is cont inuously asserting the in terrupt request, the interrupt request bit is set to 1 ag ain during the next clock cycle. the only way to clear continuous assertion inte rrupts is at the source of the interrupt (for example, in the uart or spi peripherals). th e source of the interrupt must be cleared first. after the interru pt is cleared at the source, the corresponding bit in the interrupt request register must also be cleared to 0. both the interrupt source and the irq register must be cleared.
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 48 interrupt control register definitions for all interrupts other than the watch-dog ti mer interrupt, the interru pt control registers enable individual interrupts, set interrupt priorities, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register (tab le 23) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending t2i?timer 2 interrupt request 0 = no interrupt request is pending for timer 2. 1 = an interrupt request from timer 2 is awaiting service. t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the ua rt 0 transmitter is awaiting service. table 23. interrupt requ est 0 register (irq0) bits 7 6 5 4 3 2 1 0 field t2i t1i t0i u0rxi u0txi i2ci spii adci reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc0h
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 49 i 2 ci? i 2 c interrupt request 0 = no interrupt request is pending for the i 2 c. 1 = an interrupt request from the i 2 c is awaiting service. spii?spi interrupt request 0 = no interrupt request is pending for the spi. 1 = an interrupt request from the spi is awaiting service. adci?adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. 1 = an interrupt request from the analog-t o-digital converter is awaiting service. interrupt request 1 register the interrupt request 1 (irq1) register (table 24) stores inte rrupt requests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq1 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. pad x i?port a or port d pin x interrupt request 0 = no interrupt request is pendin g for gpio port a or port d pin x . 1 = an interrupt request from gpio port a or port d pin x is awaiting service. where x indicates the specific gpio port pin number (0 through 7). for each pin, only 1 of either port a or port d can be enabled for in terrupts at any one time. port selection (a or d) is determined by th e values in the interrupt port select register. table 24. interrupt requ est 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pad7i pad6i pad5i pad4i pad3i pad2i pad1i pad0i reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc3h
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 50 interrupt request 2 register the interrupt request 2 (irq2) register (table 25) stores inte rrupt requests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq2 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. t3i?timer 3 interrupt request 0 = no interrupt request is pending for timer 3. 1 = an interrupt request from timer 3 is awaiting service. u1rxi?uart 1 receive interrupt request 0 = no interrupt request is pe nding for the uart1 receiver. 1 = an interrupt request from uart1 receiver is awaiting service. u1txi?uart 1 transmit interrupt request 0 = no interrupt request is pending for the uart 1 transmitter. 1 = an interrupt request from the ua rt 1 transmitter is awaiting service. dmai?dma interrupt request 0 = no interrupt request is pending for the dma. 1 = an interrupt request from the dma is awaiting service. pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. where x indicates the specific gpio po rt c pin number (0 through 3). table 25. interrupt requ est 2 register (irq2) bits 7 6 5 4 3 2 1 0 field t3i u1rxi u1txi dmai pc3i pc2i pc1i pc0i reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc6h
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 51 irq0 enable high a nd low bit registers the irq0 enable high and low bit registers (tables 27 and 28) form a priority encoded enabling for interrupts in the interrupt request 0 register. priority is generated by setting bits in each register. table 26 desc ribes the priority control for irq0. t2enh?timer 2 interrupt re quest enable high bit t1enh?timer 1 interrupt re quest enable high bit t0enh?timer 0 interrupt re quest enable high bit u0renh?uart 0 receive interrupt request enable high bit u0tenh?uart 0 transmit interrupt request enable high bit i2cenh?i 2 c interrupt request enable high bit spienh?spi interrupt request enable high bit adcenh?adc interrupt request enable high bit table 26. irq0 enable and priority encoding irq0enh[ x ]irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7. table 27. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field t2enh t1enh t0enh u0renh u0tenh i2cenh spienh adcenh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc1h
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 52 t2enl?timer 2 interrupt request enable low bit t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit i2cenl?i 2 c interrupt request enable low bit spienl?spi interrupt request enable low bit adcenl?adc interrupt request enable low bit irq1 enable high a nd low bit registers the irq1 enable high and low bit registers (tables 30 and 31) form a priority encoded enabling for interrupts in the interrupt request 1 register. priority is generated by setting bits in each register. table 29 desc ribes the priority control for irq1. table 28. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field t2enl t1enl t0enl u0renl u0 tenl i2cenl spienl adcenl reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc2h table 29. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7.
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 53 pad x enh?port a or port d bit[ x ] interrupt request enable high bit refer to the interrupt port sel ect register for selection of either port a or port d as the interrupt source. pad x enl?port a or port d bit[ x ] interrupt reques t enable low bit refer to the interrupt port sel ect register for selection of either port a or port d as the interrupt source. irq2 enable high a nd low bit registers the irq2 enable high and low bit registers (tables 33 and 34) form a priority encoded enabling for interrupts in the interrupt request 2 register. priority is generated by setting bits in each register. table 32 desc ribes the priority control for irq2. table 30. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pad7enh pad6enh pad5enh pad4enh pad3enh pad2enh pad1enh pad0enh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc4h table 31. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pad7enl pad6enl pad5enl pad4enl pad3enl pad2enl pad1enl pad0enl reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc5h table 32. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0 through 7.
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 54 t3enh?timer 3 interrupt re quest enable high bit u1renh?uart 1 receive interrupt request enable high bit u1tenh?uart 1 transmit interrupt request enable high bit dmaenh?dma interrupt request enable high bit c3enh?port c3 interrupt request enable high bit c2enh?port c2 interrupt request enable high bit c1enh?port c1 interrupt request enable high bit c0enh?port c0 interrupt request enable high bit t3enl?timer 3 interrupt request enable low bit u1renl?uart 1 receive interru pt request enable low bit u1tenl?uart 1 transmit interru pt request enable low bit dmaenl?dma interrupt request enable low bit c3enl?port c3 interrupt request enable low bit c2enl?port c2 interrupt request enable low bit c1enl?port c1 interrupt request enable low bit c0enl?port c0 interrupt request enable low bit interrupt edge select register the interrupt edge sele ct (irqes) register (table 35) de termines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port input pin. the table 33. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field t3enh u1renh u1tenh dmaenh c3enh c2enh c1enh c0enh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc7h table 34. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field t3enl u1renl u1tenl dmaenl c3enl c2enl c1enl c0enl reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fc8h
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 55 interrupt port select register selects between port a and port d fo r the individual inter- rupts. ies x ?interrupt edge select x where x indicates the specific gpio port pin number (0 through 7). the pulse width should be greater than 1 system clock to guar antee capture of the ed ge triggered interrupt. 0 = an interrupt request is genera ted on the falling edge of the pa x /pd x input. 1 = an interrupt request is genera ted on the rising edge of the pa x /pd x input. interrupt port select register the port select (irqps) register (table 36) determines the port pi n that generates the pax/pdx interrupts. this register allows either port a or port d pins to be used as inter- rupts. the interrupt edge select regist er controls the active interrupt edge. pad x s?pa x /pd x selection 0 = pa x is used for the interrupt for pa x /pd x interrupt request. 1 = pd x is used for the interrupt for pa x /pd x interrupt request. where x indicates the specific gpio port pin number (0 through 7). table 35. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fcdh table 36. interrupt port select register (irqps) bits 7 6 5 4 3 2 1 0 field pad7s pad6s pad5s pad4s pad3s pad2s pad1s pad0s reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fceh
ps017611-0406 interrupt controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 56 interrupt control register the interrupt control (irqctl) register (table 37) contains the master enable bit for all interrupts. irqe?interrupt request enable this bit is set to 1 by execution of an ei (enable interrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an interrupt request, or reset. 0 = interrupts are disabled. 1 = interrupts are enabled. reserved these bits must be 0. table 37. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr addr fcfh
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 timers 57 timers overview the z8f640x family products contain three to four 16-bit reloadable timers that can be used for timing, event counting, or generation of pulse-width modulated (pwm) signals. the timers? features include: ? 16-bit reload counter ? programmable prescaler with prescale values from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock ga ting, or capture signal. external input pin signal frequency is limited to a maximum of one-fourth the system clock frequency. ? timer output pin ? timer interrupt in addition to the timers described in this chapter, the baud rate generators for any unused uart, spi, or i 2 c peripherals may also be used to provide basic timing function- ality. refer to the respective serial communica tion peripheral chapters for information on using the baud rate generators as timers. ti mer 3 is unavailable in the 40- and 44-pin packages. architecture figure 66 illustrates the architecture of the timers.
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 58 figure 66. timer block diagram operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer counts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer generates an interrupt and th e count value in the timer high and low byte registers is reset to 0001h . then, the timer is automatically disabled and stops counting. also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if it is desired to have the timer output make a permanent state change upon one-shot time- 16-bit pwm / compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer timer block system timer data block interrupt output control bus clock input gate input capture input
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 59 out, first set the tpol bit in the timer control register to the start value before beginning one-shot mode. then, after starting the timer, set tpol to the opposite bit value. the steps for configuring a timer for one-s hot mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode. ? set the prescale value. ? if using the timer output alternate functio n, set the initial output level (high or low). 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always pr ovides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. al so, if the timer output alternate function is enabled, the timer outp ut pin changes state (from low to high or from high to low) upon timer reload. the steps for configuring a timer for continuo us mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode. ? set the prescale value. one-shot mode time-out period (s) reload value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------ =
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 60 ? if using the timer output alternate functio n, set the initial output level (high or low). 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this only affects the first pass in continuous mode. after the first timer reload in continuous mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock always provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first time-out period. counter mode in counter mode, the tim er counts input transitions from a gpio port pin. the timer input is taken from the gpio port pin timer input alternate function. the tpol bit in the timer control register selects whether the count occurs on the rising edge or the falling edge of the timer input signal. in counte r mode, the prescaler is disabled. the input frequency of the timer inpu t signal must not exceed one-fourth the system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. the steps for configuring a tim er for counter mode and initi ating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for counter mode. continuous mode time-out period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = caution:
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 61 ? select either the rising edge or falling edge of the timer input signal for the count. this also sets the initial logic level (hig h or low) for the timer output alternate function. however, the timer output fu nction does not have to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode . after the first timer reload in counter mode, counting always begins at the reset value of 0001h . generally, in counter mode the timer high and low byte regi sters must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer. in counter mode, the number of timer input tr ansitions since the timer start is given by the following equation: pwm mode in pwm mode, the timer output s a pulse-width modulator (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16- bit pwm match value stored in the timer pw m high and low byte registers. when the timer count value matches the pwm value, th e timer output toggles. the timer continues counting until it reaches the reload value stor ed in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and then transitions to a low (0) when the timer value ma tches the pwm value. the timer output signal returns to a high (1 ) after the timer reaches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and then transitions to a high (1) when the timer value matches the pwm value. the timer output signal returns to a low (0 ) after the timer reaches the reload value and is reset to 0001h . the steps for configuring a timer for pwm mode and initiating the pwm operation are as follows: 1. write to the timer control register to: counter mode timer input transition s current count value start value ? =
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 62 ? disable the timer ? configure the timer for pwm mode. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation must be used to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm output high time to the total period is given by: if tpol is set to 1, the ratio of the pwm output high time to the total period is given by: capture mode in capture mode, the current timer count valu e is recorded when the desired external timer input transition occurs. the capture coun t value is written to the timer pwm high and low byte registers. the timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the pwm period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ----------------------------------------------------------------------- - 100 = pwm output high time ratio (%) pwm value reload value ---------------------------------- 100 =
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 63 timer input signal. when the capture event occu rs, an interrupt is generated and the timer continues counting. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload value, th e timer generates an interrupt and continues counting. the steps for configuring a tim er for capture mode and initia ting the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows user software to determine if interrupts were generated by either a capture event or a reload. if the pwm high and lo w byte registers still contain 0000h after the interrupt, then the interrupt was generated by a reload. 5. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from time r start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to th e 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon com- pare. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- =
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 64 if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. the steps for configuring a timer for compar e mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode. ? set the prescale value. ? set the initial logic level (high or low) fo r the timer output alternate function, if desired. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in compare mode, the system clock always pr ovides the timer input. the compare time is given by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal is still asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. the steps for configuring a timer for gated mode and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer compare mode time (s) compare value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------------ =
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 65 ? configure the timer for gated mode. ? set the prescale value. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the desired transition (rising edge or falling edge) is set by the tpol bit in the timer control register. the timer input is the system clock. every subsequent desired transitio n (after the first) of the timer input signal captures the current count value. the capture value is wr itten to the timer pwm high and low byte registers. when the capture even t occurs, an interrupt is gene rated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the steps for configuring a timer for captur e/compare mode and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. if desired, enable the timer interrupt and se t the timer interrupt priority by writing to the relevant interrupt registers.
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 66 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. counting begins on the first appropriate transition of the timer input signal. no interrupt is generated by this first edge. in capture/compare mode, the elapsed time fro m timer start to capture event can be cal- culated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when the timer is enabled and the timer high byte reg- ister is read, the contents of the timer low byte register are placed in a holding register. a subsequent read from the timer low byte register returns the value in the holding register. this operation allows accurate reads of the full 16-bit time r count value while enabled. when the timers are not enabled, a read fro m the timer low byte register returns the actual value in the counter. timer output signal operation timer output is a gpio port pin alternate func tion. generally, the timer output is toggled every time the counter is reloaded. timer control register definitions timers 0?2 are available in all packages. time r 3 is available only in the 64-, 68- and 80- pin packages. timer 0-3 high and low byte registers the timer 0-3 high and low byte (txh and tx l) registers (tables 38 and 39) contain the current 16-bit timer count value. when the tim er is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from tmrl always returns this temporary register when the timers are enabled. when the timer is disabled, reads from the tmrl reads the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- =
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 67 written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the counte r continues counting from the new value. th and tl?timer high and low bytes these 2 bytes, {tmrh[7:0], tmrl[7:0]}, cont ain the current 16-bit timer count value. timer reload high and low byte registers the timer 0-3 reload high and low byte (txrh and txrl) registers (tables 40 and 41) store a 16-bit reload value, {trh[7:0], trl[ 7:0]}. values written to the timer reload high byte register are stored in a temporar y holding register. when a write to the timer reload low byte register occurs, the temporar y holding register value is written to the timer high byte register. this operation a llows simultaneous updates of the 16-bit timer reload value. in compare mode, the timer reload high an d low byte registers store the 16-bit com- pare value. in single-byte dma transactions to the time r reload high byte register, the temporary holding register is bypassed an d the value is written directly to the register. if the dma is table 38. timer 0-3 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f00h, f08h, f10h, f18h table 39>. timer 0-3 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f01h, f09h, f11h, f19h
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 68 set to 2-byte transfers, the te mporary holding register for the timer reload high byte is not bypassed. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], tr l[7:0]}. this value is used to set the maximum co unt value which initiate s a timer reload to 0001h . in compare mode, these two byte form the 16-bit compare value. table 40. timer 0-3 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f02h, f0ah, f12h, f1ah table 41. timer 0-3 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f03h, f0bh, f13h, f1bh
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 69 timer 0-3 pwm high and low byte registers the timer 0-3 pwm high and low byte (t xpwmh and txpwml) registers (tables 42 and 43) are used for pulse-width modulator (p wm) operations. these registers also store the capture values for the capture and capture/compare modes. pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl) register. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. table 42. timer 0-3 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f04h, f0ch, f14h, f1ch table 43. timer 0-3 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f05h, f0dh, f15h, f1dh
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 70 timer 0-3 control registers the timer 0-3 control (txctl) registers enab le/disable the timers, set the prescaler value, and determine the timer operating mode. ten?timer enable 0 = timer is disabled. 1 = timer enabled to count. tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. pwm mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced hi gh (1) upon pwm count matc h and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. table 44. timer 0-3 control register (txctl) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f07h, f0fh, f17h, f1fh
ps017611-0406 timers z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 71 capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the ti mer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent risi ng edges of the timer input signal. 1 = counting is started on the first falling ed ge of the timer input signal. the current count is captured on subsequent fa lling edges of the timer input signal. pres?prescale value. the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this insures proper clock division each time the timer is restarted. 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 tmode?timer mode 000 = one-shot mode 001 = continuous mode 010 = counter mode 011 = pwm mode 100 = capture mode 101 = compare mode 110 = gated mode 111 = capture/compare mode
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 watch-dog timer 72 watch-dog timer overview the watch-dog timer (wdt) help s protect against corrupt or unreliable software, power faults, and other system-level problems which may place the z8 encore! ? into unsuitable operating states. the watch-dog time r includes the following features: ? on-chip rc oscillator ? a selectable time-out response: short reset or interrupt ? 24-bit programmable time-out value operation the watch-dog timer (wdt) is a retriggerable on e-shot timer that resets or interrupts the z8f640x family device when the wdt reaches its terminal count. the watch-dog timer uses its own dedicated on-chip rc oscillator as its clock source. the watch-dog timer has only two modes of operation?on and off. once enabled, it always counts and must be refreshed to prevent a time-out. an enab le can be performed by executing the wdt instruction or by setting the wdt_ao option bit. the wdt_ao bit enables the watch-dog timer to operate all the time, even if a wdt instruction has not been executed. the watch-dog timer is a 24-bit reloadable do wncounter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is given by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watch-dog timer rc oscillator frequency is 50khz. the watch-dog timer cannot be refreshed once it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 45 provides wdt time-out period (ms) wdt reload value 50 ----------------- ------------------ -------------- - =
ps017611-0406 watch-dog timer z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 73 information on approximate time-out delays for the minimum and maximum wdt reload values. watch-dog timer refresh when first enabled, the watch-dog timer is loaded with the value in the watch-dog timer reload registers. the watch- dog timer then counts down to 000000h unless a wdt instruction is executed by the ez8 cp u. execution of the wdt instruction causes the downcounter to be reloaded with the wdt reload value stored in the watch-dog timer reload registers. counting resu mes following the reload operation.\ when the z8f640x family device is opera ting in debug mode (via the on-chip debug- ger), the watch-dog timer is continuously refreshed to prevent spurious watch-dog timer time-outs. watch-dog timer time-out response the watch-dog timer times out when the counter reaches 000000h . a time-out of the watch-dog timer generates either an interrupt or a short reset. the wdt_res option bit determines the time-out response of th e watch-dog timer. refer to the option bits chap- ter for information regard ing programming of the wdt_res option bit. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occurs, the watch-dog timer issues an interrupt request to the in terrupt controller and sets the wdt status bit in the watch-dog timer control register. if interrupts are enable d, the ez8 cpu respon ds to the interrupt request by fetching the watch-dog timer interrupt vector and executing code from the vector address. after time-out and interrupt generation, the watch-dog timer counter rolls over to its maximum value of fffffh and continues counting. the watch-dog timer counter is not automatically returned to its reload value. wdt interrupt in stop mode if configured to generate an interrupt when a time-out oc curs and the z8f640x family device is in stop mode, the watch-dog timer automatically initiates a stop mode recovery and generates an in terrupt request. both the wdt status bit and the stop bit in the watch-dog timer control register are set to 1 following wdt time-out in stop table 45. watch-dog timer approximate time-out delays wdt reload value wdt reload value approximate time-out delay (with 50khz typical wdt oscillator frequency) (hex) (decimal) typical description 000004 4 80 s minimum time-out delay ffffff 16,777,215 335.5s maximum time-out delay
ps017611-0406 watch-dog timer z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 74 mode. refer to the reset and stop mode recovery chapter for more information on stop mode recovery. if interrupts are enabled, following completi on of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watch-dog timer interrupt vector and executing code from the vector address. wdt reset in normal operation if configured to generate a re set when a time-out occurs, th e watch-dog timer forces the z8f640x family device into the short reset state. the wdt status bit in the watch-dog timer control register is set to 1. refer to the reset and stop mode recovery chapter for more information on short reset. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the z8f640x family device is in stop mode, the watch-dog timer initia tes a stop mode recovery. both the wdt sta- tus bit and the stop bit in the watch-dog timer contro l register are set to 1 following wdt time-out in stop mode. refer to the reset and stop mode recovery chapter for more information. watch-dog timer reload unlock sequence writing the unlock sequence to the watch- dog timer control register (wdtctl) unlocks the three watch-dog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time- out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. the follow se quence is required to unlock the watch-dog timer reload byte regist ers (wdtu, wdth, and wdtl) for write access. 1. write 55h to the watch-dog ti mer control register (wdtctl) 2. write aah to the watch-dog ti mer control register (wdtctl) 3. write the watch-dog timer relo ad upper byte register (wdtu) 4. write the watch-dog timer relo ad high byte register (wdth) 5. write the watch-dog timer reload low byte register (wdtl) all three watch-dog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no fu rther writes can occur, unless the sequence is restarted. the value in the watch-dog timer reload registers is loaded into the counter when the watch-dog timer is first enabled an d every time a wdt instruction is executed.
ps017611-0406 watch-dog timer z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 75 watch-dog timer control register definitions watch-dog timer control register the watch-dog timer control (w dtctl) register, detailed in table 46, is a read-only register that indicates the source of the most recent reset event, indicates a stop mode recovery event, and indicates a watch-dog ti mer time-out. reading this register resets the upper four bits to 0. writing the 55h , aah unlock sequence to the watch- dog timer control (wdtctl) reg- ister address unlocks the three watch-dog ti mer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism preven ts spurious writes to the reload registers. por?power-on reset indicator if this bit is set to 1, a power-on reset event occurred. this bit is reset to 0 if a wdt time- out or stop mode recovery occurs. this bit is also reset to 0 when the register is read. stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurred. if the stop and wdt bits are both set to 1, the stop mode recovery occurred due to a wdt time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a power-on reset or a wdt time-out that occurred while not in stop mode. reading this register also resets this bit. wdt?watch-dog timer time-out indicator if this bit is set to 1, a wdt time-out occurred. a power-on reset resets this pin. a stop mode recovery from a change in an input pin also resets this bit. reading this register resets this bit. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. table 46. watch-dog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset xxx00000 r/w rrrrrrrr addr ff0
ps017611-0406 watch-dog timer z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 76 reserved these bits are reserved and must be 0. watch-dog timer reload upper, high and low byte registers the watch-dog timer reload upper, high and low byte (wdtu, wdth, wdtl) reg- isters (tables 47 through 49) form the 24-bit re load value that is lo aded into the watch- dog timer when a wdt instruction executes . the 24-bit reload value is {wdtu[7:0], wdth[7:0], wdtl[7:0]. writing to these registers sets the desired reload value. read- ing from these registers returns the current watch-dog timer count value. the 24-bit wdt reload value must not be set to a value less than 000004h or unpredictable behavior may result. wdtu?wdt reload upper byte most significant byte (msb), bits[23: 16], of the 24-bit wdt reload value. wdth?wdt reload high byte table 47. watch-dog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset 11111111 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff1h r/w* - read returns the current wdt count va lue. write sets the desired reload value. table 48. watch-dog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 11111111 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff2h r/w* - read returns the curr ent wdt count value. write sets the desired reload value. caution:
ps017611-0406 watch-dog timer z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 77 middle byte, bits[15:8], of the 24-bit wdt reload value. wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 24-bit wdt reload value. table 49. watch-dog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 11111111 r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff3h r/w* - read returns the curr ent wdt count value. write sets the desired reload value.
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 uart 78 uart overview the universal asynchronous receiver/transmitter (uart) is a full-duplex communica- tion channel capable of handling asynchronous data transfers. the z8f640x family device contains two fully independent uarts. the uart uses a single 8-bit data mode with selectable parity. features of the uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun and break detection ? separate transmit and receive enables ? selectable 9-bit multiprocessor (9-bit) mode ? 16-bit baud rate generator (brg) architecture the uart consists of three primary functional blocks: transmitter, rece iver, and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figure 67 illustrates the uart architecture.
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 79 operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit can be optio nally added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 67. uart block diagram receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control register transmitter control cts status register register register register baud rate generator
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 80 figures 68 and 69 illustrates the asynchronous data format employed by the uart with- out parity and with parity, respectively. transmitting data using the polled method follow these steps to transmit data us ing the polled method of operation: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiprocessor (9 -bit) mode functions, if desired. 4. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? enable parity, if desired, and select either even or odd parity. ? set or clear the ctse bit to enable or disable cont rol from the receiver using the cts pin. figure 68. uart asynchronous data format without parity figure 69. uart asynchronous data format with parity start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 81 5. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 6. if the transmit data register is full (indicated by a 0), continue to monitor the tdre bit until the transmit data register becomes available to receive new data. 6. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit shift register and transmit the data. 7. to transmit additional b its, return to step 5. transmitting data using th e interrupt-driven method the uart transmitter interrupt indicates the ava ilability of the transmit data register to accept new data for transmission. follow these steps to configure the uart for interrupt- driven data transmission: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the desired priority. 5. write to the uart control 1 register to enable multiprocessor (9 -bit) mode functions, if desired. 6. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? enable parity, if desired, and select either even or odd parity. ? set or clear the ctse bit to enable or disable control from the receiver via the cts pin. 7. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-driven data transmission. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) should per- form the following: 8. write the data byte to the uart tran smit data register. the transmitter will automatically transfer the data to the tran smit shift register and transmit the data. 9. clear the uart transmit interrupt bit in th e applicable interrupt request register. 10. execute the iret instruction to return fro m the interrupt-service routine and wait for the transmit data register to again become empty.
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 82 receiving data using the polled method follow these steps to configure th e uart for polled data reception: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiprocessor (9 -bit) mode functions, if desired. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if desired, and select either even or odd parity. 5. check the rda bit in the uart status 0 register to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 6. if the rece ive data register is empty (indicated by a 0), continue to monitor the rda bit awaiting reception of the valid data. 6. read data from the uart receive data re gister. if operating in multiprocessor (9-bit) mode, first read the multip rocessor receive flag ( mprx ) to determine if the data was directed to this uart before reading the data. 7. return to step 6 to receive additional data. receiving data using the interrupt-driven method the uart receiver interrupt indicates the av ailability of new data (as well as error con- ditions). follow these steps to configure the uart receiver for interrupt-driven operation: 1. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the desired priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9 -bit) mode functions, if desired.
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 83 7. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if desired, and select either even or odd parity. 8. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service routine (isr) should per- form the following: 9. check the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 10. if the interrupt was due to data availabl e, read the data from the uart receive data register. if operating in multiprocessor (9 -bit) mode, first read the multiprocessor receive flag ( mprx ) to determine if the data was directed to this uart before reading the data. 11. clear the uart receiver interrupt in th e applicable interrupt request register. 12. execute the iret instruction to return from the interrupt-servi ce routine and await more data. receiving data using the direct memory access c ontroller (dma) the dma and uart can coordinate automatic data transfer from the uart receive data register to general-purpose register f ile ram. this reduces the ez8 cpu process- ing overhead required to support uart data reception. the uart receiver interrupt must then only notify the ez8 cpu of error conditions. follow these st eps to configure the uart and dma for automatic data handling: 1. write to the dma control registers to co nfigure the dma to transfer data from the uart receive data register to general-purpose register file ram. 2. write to the uart baud rate high and lo w byte registers to set the desired baud rate. 3. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the desired priority. 5. write to the uart control 1 register to: ? enable multiprocessor (9-bit) mode functions, if desired. ? disable the uart interrupt for received data by clearing rdairq to 0.
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 84 6. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if desired, and select either even or odd parity. the uart and dma are now configured for data reception and automatic data transfer to the register file. when a valid data byte is received by the uart the following occurs: 7. the uart notifies the dma controller that a data byte is available in the uart receive data register. 8. the dma controller requests control of the system bus from the ez8 cpu. 9. the ez8 cpu acknowledges the bus request. 10. the dma controller transfers the data from the uart receive data register to another location in ram and then retu rn bus control back to the ez8 cpu. the uart and dma can continue to transf er incoming data bytes without ez8 cpu intervention. when a uart error is detected, the uart receiver interrupt is generated. the associated interrupt service rout ine (isr) should perfo rm the following: 11. check the uart status 0 register to dete rmine the source of the uart error or break condition and then respond appropriately. multiprocessor (9-bit) mode the uart has a multiprocessor mode that uses an extra (9 th) bit for selective communi- cation when a number of processors share a common uart bus. in multiprocessor (9-bit) mode (also referred to as 9-bit mode), the multiprocessor bit (mp) is transmitted immedi- ately following the 8-bits of data and immedi ately preceding the stop bit(s) as illustrated in figure 70. the character format is: in multiprocessor (9-bit) mode, parity is not an option as the parity bit location (9th bit) becomes the multiprocessor contro l bit. the uart control 1 and status 1 registers pro- vide multiprocessor (9-bit) mode control and status information. figure 70. uart asynchronous multip rocessor (9-bit) mode data format start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 85 uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disable d, the baud rate generator can also func- tion as a basic timer with interrupt capability. transmitter interrupts the transmitter generates an interrupt any time the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to acce pt new data for trans- mission. writing to the uart transmit data register clears the uart transmit interrupt. receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte has been received and is av ailable in the uart receive data register. this interrupt can be disabled independent of the other receiver interrupt sources. ? a break is received. ? an overrun is detected. ? a data framing error is detected. baud rate generator interrupts if the baud rate generator (brg) interrupt en able is set, the uart receiver interrupt asserts when the uart baud rate generator re loads. this action a llows the baud rate generator to function as an ad ditional counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is th e system clock. the uart x baud rate high and low byte registers combine to cr eate a 16-bit baud rate divisor value (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate ge nerator can function as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the uart by clearing the ren and ten bits in the uart control 0 register to 0. 2. load the desired 16-bit co unt value into the uart baud rate high and low byte registers. uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value -------------------- --------------------- ---------------------- ----------------- -------------- =
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 86 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the uart x control 1 register to 1. uart control register definitions the uart control registers support both th e uarts and the associated infrared encoder/ decoders. for more info rmation on the infrared op eration, refer to the infrared encoder/ decoder chapter on page 95. uart x transmit data register data bytes written to the uart x transmit data register (table 50) are shifted out on the txd x pin. the write-only uart x transmit data register shares a register file address with the read-only uart x receive data register. txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. table 50. uart x transmit data register (u x txd) bits 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww addr f40h and f48h
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 87 uart x receive data register data bytes received through the rxd x pin are stored in the uart x receive data register (table 51). the read-only uart x receive data register shares a register file address with the write-only uart x transmit data register. rxd?receive data uart receiver data byte from the rxd x pin uart x status 0 and st atus 1 registers the uart x status 0 and status 1 registers (table 52 and 53) identify the current uart operating configuration and status. rda?receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. pe?parity error this bit indicates that a parity error has occurred. reading the uart receive data regis- ter clears this bit. table 51. uart x receive data register (u x rxd) bits 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr addr f40h and f48h table 52. uart x status 0 register (u x stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 000001 1x r/w rrrrrr r r addr f41h and f49h
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 88 0 = no parity error has occurred. 1 = a parity error has occurred. oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, then reading the uart receive da ta register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multip rocessor bit, and stop bit(s) are all zeros then this bit is set to 1. reading the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmit- ted. txe?transmitter empty this bit indicates that the transmit shift regist er is empty and character transmission is fin- ished. 0 = data is currently transmitting. 1 = transmission is complete. cts?cts signal when this bit is read it re turns the level of the cts signal.
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 89 reserved these bits are reserved and must be 0. mprx?multiprocessor receive this status bit is for the receiver and reflects the actual status of the last multiprocessor bit received. reading from the uart data register resets this bit to 0. uart x control 0 and control 1 registers the uart x control 0 and control 1 registers (tab les 54 and 55) configure the properties of the uart?s transmit and receive operations . the uart control registers must ben be written while the uart is enabled. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. table 53. uart x status 1 register (u x stat1) bits 7 6 5 4 3 2 1 0 field reserved mprx reset 000000 0 0 r/w rrrrrr r r addr f44h and f4ch table 54. uart x control 0 register (u x ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f42h and f4ah
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 90 ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. 0 = parity is disabled. 1 = the transmitter sends data with an additio nal parity bit and the receiver receives an additional parity bit. psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted an d expected on all received data. sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so insure that the transmitter has finished sending data before setting this bit. 0 = no break is sent. 1 = the output of the transmitter is zero. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver. birq?baud rate genera tor interrupt request this bit sets an interrupt requ est when the baud rate generato r times out and is only set if a uart is not enabled. the is bit produces no effect when the uart is enabled. 0 = interrupts behave as set by uart control. 1 = the baud rate generator generates a receive interrupt when it counts down to zero. mpm?multiprocessor (9-bit) mode select this bit is used to enable multiprocessor (9-bit) mode. table 55. uart x control 1 register (u x ctl1) bits 7 6 5 4 3 2 1 0 field birq mpm mpe mpbt reserved rdairq iren reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f43h and f4bh
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 91 0 = disable multiprocessor mode. 1 = enable multiprocessor mode. mpe?multiprocessor enable 0 = the uart processes all received data bytes. 1 = the uart processes only data bytes in which the multiproces sor data bit (9th bit) is set to 1. mpbt?multiprocessor bit transmitter this bit is applicable only when mu ltiprocessor (9-bit) mode is enabled. 0 = send a 0 in the multipro cessor bit location of the data stream (9th bit). 1 = send a 1 in the multipro cessor bit location of the data stream (9th bit). reserved these bits are reserved and must be 0. rdairq ?receive data interrupt enable 0 = received data and receiver errors generat es an interrupt request to the interrupt con- troller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. the associated dma will still be notified that received data is available. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is disabled . uart operates normally operation. 1 = infrared encoder/decoder is enabled. the uart transmits and r eceives data through the infrared en coder/decoder. uart x baud rate high and low byte registers the uart x baud rate high and low byte regist ers (tables 56 and 57) combine to create a 16-bit baud rate divisor value (brg[15:0]) that sets the data tr ansmission rate (baud rate) of the uart. table 56. uart x baud rate high byte register (u x brh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f46h and f4eh
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 92 the uart data rate is calcula ted using the following equation: for a given uart data rate, the integer baud ra te divisor value is calculated using the fol- lowing equation: the baud rate error relative to the desired baud rate is calcu lated using the following equa- tion: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 58 provides information on data rate e rrors for popular baud rates and commonly used crystal osc illator frequencies. table 57. uart x baud rate low byte register (u x brl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f47h and f4fh uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- --------------------- --------------------- ------------------ --------------- = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) ------------------- --------------------- --------------------- --------------- ? ? ? ? = uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ------------------- --------------------- --------------------- ------------------ ----------------- - ?? ?? =
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 93 table 58. uart baud rates 20.0 mhz system clock 18.432 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 1 1250.0 0.00 1250.0 1 1152.0 -7.84% 625.0 2 625.0 0.00 625.0 2 576.0 -7.84% 250.0 5 250.0 0.00 250.0 5 230.4 -7.84% 115.2 11 113.6 -1.36 115.2 10 115.2 0.00 57.6 22 56.8 -1.36 57.6 20 57.6 0.00 38.4 33 37.9 -1.36 38.4 30 38.4 0.00 19.2 65 19.2 0.16 19.2 60 19.2 0.00 9.60 130 9.62 0.16 9.60 120 9.60 0.00 4.80 260 4.81 0.16 4.80 240 4.80 0.00 2.40 521 2.40 -0.03 2.40 480 2.40 0.00 1.20 1042 1.20 -0.03 1.20 960 1.20 0.00 0.60 2083 0.60 0.02 0.60 1920 0.60 0.00 0.30 4167 0.30 -0.01 0.30 3840 0.30 0.00 16.667 mhz system clock 11.0592 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 1 1041.69 -16.67 1250.0 n/a n/a n/a 625.0 2 520.8 -16.67 625.0 1 691.2 10.59 250.0 4 260.4 4.17 250.0 3 230.4 -7.84 115.29115.70.47115.26115.20.00 57.6 18 57.87 0.47 57.6 12 57.6 0.00 38.4 27 38.6 0.47 38.4 18 38.4 0.00 19.2 54 19.3 0.47 19.2 36 19.2 0.00 9.60 109 9.56 -0.45 9.60 72 9.60 0.00 4.80 217 4.80 -0.83 4.80 144 4.80 0.00 2.40 434 2.40 0.01 2.40 288 2.40 0.00 1.20 868 1.20 0.01 1.20 576 1.20 0.00 0.60 1736 0.60 0.01 0.60 1152 0.60 0.00 0.30 3472 0.30 0.01 0.30 2304 0.30 0.00
ps017611-0406 uart z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 94 10.0 mhz system clock 5.5296 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 -16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 -1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 -0.03 2.40 144 2.40 0.00 1.20 521 1.20 -0.03 1.20 288 1.20 0.00 0.60 1042 0.60 -0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.02 0.30 1152 0.30 0.00 3.579545 mhz system clock 1.8432 mhz system clock desired rate brg divisor actual rate error desired rate brg divisor actual rate error (khz) (decimal) (khz) (%) (khz) (decimal) (khz) (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 -10.51 250.0 n/a n/a n/a 115.2 2 111.9 -2.90 115.2 1 115.2 0.00 57.6 4 55.9 -2.90 57.6 2 57.6 0.00 38.4 6 37.3 -2.90 38.4 3 38.4 0.00 19.2 12 18.6 -2.90 19.2 6 19.2 0.00 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 -0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 -0.04 0.60 192 0.60 0.00 0.30 746 0.30 -0.04 0.30 384 0.30 0.00 table 58. uart baud rates (continued)
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 infrared encoder/decoder 95 infrared encoder/decoder overview the z8f640x family products contain two fully-functional, high-performance uart to infrared encoder/de coders (endecs). each infrared endec is integrated with an on-chip uart to allow easy communication between the z8f640x family device and irda phys- ical layer specification version 1.3-compli ant infrared transceivers. infrared communica- tion provides secure, reliable, low-cost, po int-to-point communication between pcs, pdas, cell phones, printers and other infrared enabled devices. architecture figure 71 illustrates the archite cture of the infrared endec. figure 71. infrared data communi cation system block diagram interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec) zilog zhx1810
ps017611-0406 infrared encoder/decoder z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 96 operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infra- red transceiver via the txd pin. likewise, da ta received from the in frared transceiver is passed to the infrared endec via the rxd pin, decoded by the infrared endec, and then passed to the uart. communication is hal f-duplex, which means simultaneous data transmission and reception is not allowed. the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enabled to use the infrared endec. the infrared endec data rate is calculated us ing the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16-clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16-clock period. if the data to be transmi tted is 0, a 3-clock high pulse is output following a 7-clock low period. after the 3-clock high pulse, a 6-clock low pulse is output to complete the full 16 -clock data period. figure 72 illustrates irda data transmis- sion. when the infrared endec is enabled, the uart?s txd signal is internal to the z8f640x family device while the ir_txd signal is output through the txd pin. infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value --------------------- --------------------- ------------------ ------------------ ---------------- =
ps017611-0406 infrared encoder/decoder z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 97 figure 72. infrared data transmission receiving irda data data received from the infrared transceiver via the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared data bit is 16-c locks wide. figure 73 illustrates data recep- tion. when the infrared endec is enabled, the uart?s rxd signal is internal to the z8f640x family device while the ir_rxd si gnal is received through the rxd pin. baud rate ir_txd uart?s 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3-clock pulse txd clock
ps017611-0406 infrared encoder/decoder z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 98 figure 73. infrared data reception jitter because of the inherent sampling of the recei ved ir_rxd signal by the bit rate clock, some jitter can be expected on the first bit in any sequence of data. a ll subsequent bits in the received data stream are a fixed 16-clock periods wide. infrared encoder/decoder co ntrol register definitions all infrared endec configuration and status information is set by the uart control regis- ters as defined beginning on page 86 . to prevent spurious signals during irda data transmission, set the iren bit in the uart x control 1 register to 1 to enable the infrared encoder/ decoder before enabling the gpio port alte rnate function for the corre- sponding pin. baud rate uart?s ir_rxd 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8-clock delay clock rxd 16-clock period 16-clock period 16-clock period 16-clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.6 s pulse caution:
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 serial peripheral interface 99 serial peripheral interface overview the serial peripheral interface tm (spi) is a synchronous inte rface allowing several spi- type devices to be interconnected. spi-com patible devices include eeproms, analog-to- digital converters, and isdn devices. features of the spi include: ? full-duplex, synchronous, character-oriented communication ? four-wire interface ? data transfers rates up to a maximum of one-fourth the system clock frequency ? error detection ? write and mode co llision detection ? dedicated baud rate generator architecture the spi may be configured as either a master (in single or multi-master systems) or a slave as illustrated in figures 74 through 76. figure 74. spi configured as a master in a single master, single slave system spi master 8-bit shift register bit 7 bit 0 miso mosi sck ss to slave?s ss pin from slave to slave to slave baud rate generator
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 100 figure 75. spi configured as a master in a single master, multiple slave system figure 76. spi configured as a slave operation the spi is a full-duplex, synchronous, characte r-oriented channel that supports a four-wire interface (serial clock, transmit, receive and sl ave select). the spi block consists of trans- spi master 8-bit shift register bit 7 bit 0 miso mosi sck gpio to slave #2?s ss pin from slave to slave to slave ss baud rate generator vcc gpio to slave #1?s ss pin spi slave 8-bit shift register bit 7 bit 0 miso mosi sck ss from master to master from master from master
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 101 mitter and receiver sections, a baud rate (clo ck) generator and a control unit. the trans- mitter and receiver sections use the same clock. during an spi transfer, data is sent and recei ved simultaneously by both the master and the slave spi devices. separate signals are requ ired for data and the serial clock. when an spi transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an multi-bit character is simultaneou sly shifted in on a second data pin. an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular buffer. the spi shift register is single-buffered in th e transmit and receive directions. new data to be transmitted cannot be written into the shift register until the previous transmission is complete and receive data (if valid) has been read. spi signals the four basic spi signals are: ? miso (master-in, slave-out) ? mosi (master-out, slave-in) ? sck (spi serial clock) ? ss (slave select) the following paragraphs discuss these spi signal s. each signal is de scribed in both mas- ter and slave modes. master-in, slave-out the master-in, slave-out (miso) pin is config ured as an input in a master device and as an output in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. the miso pin of a slave device is placed in a high-impedance state if the slave is not selected. when the sp i is not enabled, this signal is in a high- impedance state. master-out, slave-in the master-out, slave-in (mosi) pin is configur ed as an output in a master device and as an input in a slave device. it is one of the tw o lines that transfer serial data, with the most significant bit sent first. when the spi is not enabled, this signal is in a high-impedance state. serial clock the serial clock (sck) is used to synchron ize data movement both in and out of the device through its mosi and miso pins. in master mode, the spi?s baud rate generator creates the serial clock. the master drives the serial clock out its own sck pin to the slave?s sck pin. when the spi is configured as a slave, the sck pin is an input and the clock signal from the master synchronizes th e data transfer between the master and slave devices. slave devices ignore the sck signal, unless the ss pin is asserted.
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 102 the master and slave are each capable of exchanging a byte of data during a sequence of eight clock cycles. in both master and slave sp i devices, data is shifted on one edge of the sck and is sampled on the oppos ite edge where data is stable . edge polarity is determined by the spi phase and polarity control. slave select the active low slave select (ss ) input signal is used to select a slave spi device. ss must be low prior to all data commun ication to and from the slave device. ss must stay low for the full duration of eac h character transferred. the ss signal may stay low dur- ing the transfer of multiple characters or may deassert between each character. when the spi on the z8 f640x family device is configured as the only master in an spi system, the ss pin can be set as either an input or an output. for communication between the z8f640x family device spi master and external slave devices, the ss signal, as an output, can assert the ss input pin on one of the slave devices. other gpio output pins can also be employed to select external spi slave devices. when the spi on the z8f640x family device is configured as one master in a multi-master spi system, the ss pin on the should be set as an input. the ss input signal on the master must be high. if the ss signal goes low (indicating another master is driving the spi bus), a mode fault error flag is set in the spi status register. spi clock phase and polarity control the spi supports four combinations of serial cl ock phase and polarity using two bits in the spi control register. the clock polarity bit, clkpol , selects an active high or active low clock and has no effect on the transfer format. table 59 lists the spi clock phase and polarity operation parameters. the clock phase bit, phase , selects one of two fundamen- tally different transfer formats. for proper da ta transmission, the clock phase and polarity must be identical for the spi master and the spi slave. the master always places data on the mosi line a half-cycle befo re the clock edge (sck signal ), in order for the slave to latch the data. table 59. spi clock phase ( phase ) and clock polarity ( clkpol ) operation phase clkpol sck transmit edge sck receive edge sck idle state 0 0 falling rising low 0 1 rising falling high 1 0 rising falling low 1 1 falling rising high
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 103 transfer format phase equals zero figure 77 illustrates the timing diag ram for an spi transfer in which phase is cleared to 0. the two sck waveforms show polarity with clkpol reset to 0 and with clkpol set to one. the diagram may be interpreted as either a master or slave timing diagram since the sck master-in/slave-out (m iso) and master-out/slave-in (mosi) pins are directly connected between the master and the slave. figure 77. spi timing when phase is 0 transfer format phase equals one figure 78 illustrates the timing diag ram for an spi transfer in which phase is one. two waveforms are depicted for sck, one for clkpol reset to 0 and another for clkpol set to 1. sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 104 figure 78. spi timing when phase is 1 multi-master operation in a multi-master spi system, all sck pins are tied together, all mosi pins are tied together and all miso pins are tied together. all spi pins must then be configured in open-drain mode to prevent bus contention. at any one time, only one spi device is con- figured as the master and all other spi devic es on the bus are configured as slaves. the master enables a single slave by asserting the ss pin on that slave only. then, the single master drives data out its sck and mosi pins to the sck and mosi pins on the slaves (including those which are not enabled). the en abled slave drives data out its miso pin to the miso master pin. for a master device operating in a multi-master system, if the ss pin is configured as an input and is driven low by another master, the col bit is set to 1 in the spi status regis- ter. the col bit indicates the occurrence of a multi- master collision (mode fault error con- dition). sck (clkpol = 0) sck (clkpol = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mosi bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 miso input sample time ss
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 105 error detection the spi contains error detection logic to support spi communication protocols and recog- nize when communication errors have occurred. the spi status register indicates when a data transmission error has been detected. overrun (write collision) an overrun error (write collisi on) indicates a write to the spi data register was attempted while a data transfer is in progress. an overrun sets the ovr bit in the spi status register to 1. writing a 1 to ovr clears this error flag. mode fault (multi-master collision) a mode fault indicates when mo re than one master is trying to communicate at the same time (a multi-master collision). the mode fault is detected when the enabled master?s ss pin is asserted. a mode fault sets the col bit in the spi status register to 1. writing a 1 to col clears this error flag. spi interrupts when spi interrupts are enabled, the spi gene rates an interrupt afte r data transmission. the spi in master mode generates an interrupt after a character has been sent. a character can be defined to be 1 through 8 bits by the numbits field in the spi mode register. the spi in slave mode generates an interrupt when the ss signal deasserts to indicate comple- tion of the data transfer. writing a 1 to the irq bit in the spi status register clears the pending interrupt request. if the spi is disa bled, an spi interrupt can be generated by a baud rate generator time-out. spi baud rate generator in spi master mode, the baud rate genera tor creates a lower frequency serial clock (sck) for data transmission synchronization between the master and the external slave. the input to the baud rate ge nerator is the system clock. the spi baud rate high and low byte registers combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. the reload value mu st be greater than or equal to 0002h for spi operation (maximum baud rate is system clock frequency divided by 4). the spi baud rate is calcu- lated using the following equation: when the spi is disabled, the baud rate generator can function as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: spi baud rate (bits/s) system clock frequency (hz) 2 brg[15:0] ------------------- ---------------------- --------------------- -------------- =
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 106 1. disable the spi by clearing the spien bit in the spi control register to 0. 2. load the desired 16-bit co unt value into the spi baud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the spi control register to 1. spi control register definitions spi data register the spi data register stores both the outgoing (transmit) data and the incoming (received) data. reads from the spi data register always re turn the current contents of the 8-bit shift register. with the spi configured as a master, writing a da ta byte to this register initiates the data transmission. with the spi conf igured as a slave, writing a data byte to this register loads the shift register in preparation for the next data transfer with the external master. in either the master or slave modes, if a transmission is already in progress, writes to this register are ignored and the overrun error flag, ovr , is set in the spi status register. when the character length is le ss than 8 bits (as set by the numbits field in the spi mode register), the transmit character must be left justified in the spi data register. a received character of less than 8 bits will be right justif ied. for example, if th e spi is configured for 4-bit characters, the transmit characters must be written to spidata[7:4] and the received characters are read from spidata[3:0]. data?data transmit and/or receive data. table 60. spi data register (spidata) bits 7 6 5 4 3 2 1 0 field data reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f60h
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 107 spi control register the spi control register configures the spi for transmit and receive operations. irqe?interrupt request enable 0 = spi interrupts are disabled. no interrupt requests are sent to the interrupt controller. 1 = spi interrupts are enabled. interrupt re quests are sent to the interrupt controller. str?start an spi interrupt request 0 = no effect. 1 = setting this bit to 1 also sets the irq bit in the spi status register to 1. setting this bit forces the spi to send an interrupt request to the interrupt contro l. this bit can be used by software for a function similar to transmit buffer empty in a uart. birq?brg timer interrupt request if the spi is enabled, this bit h as no effect. if the spi is disabled: 0 = the baud rate generator timer function is disabled. 1 = the baud rate generator timer func tion and time-out interrupt are enabled. phase?phase select sets the phase relationship of the da ta to the clock. refer to the spi clock phase and polarity control section for more inform ation on operation of the phase bit. clkpol?clock polarity 0 = sck idles low (0). 1 = sck idle high (1). wor?wire-or (open-drain) mode enabled 0 = spi signal pins not configured for open-drain. 1 = all four spi signal pins (sck, ss , miso, mosi) configured for open-drain function. this setting is typically used for multi- master and/or multi-sl ave configurations. mmen?spi master mode enable 0 = spi configured in slave mode. 1 = spi configured in master mode. table 61. spi control register (spictl) bits 7 6 5 4 3 2 1 0 field irqe str birq phase clkpol wor mmen spien reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f61h
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 108 spien?spi enable 0 = spi disabled. 1 = spi enabled. spi status register the spi status register indicates the current state of the spi. irq?interrupt request 0 = no spi interrupt request pending. 1 = spi interrupt request is pending. ovr?overrun 0 = an overrun error has not occurred. 1 = an overrun error has been detected. col?collision 0 = a multi-master collision (m ode fault) has not occurred. 1 = a multi-master collision (mod e fault) has been detected. reserved these bits are reserved and must be 0. txst?transmit status 0 = no data transmission currently in progress. 1 = data transmission cu rrently in progress. slas?slave select if spi enabled as a slave, 0 = ss input pin is asserted (low) 1 = ss input is not asserted (high). if spi enabled as a master, th is bit is not applicable. table 62. spi status register (spistat) bits 7 6 5 4 3 2 1 0 field irq ovr col reserved txst slas reset 000 0 0 1 r/w r/w* r/w* r/w* r r r addr f62h r/w* = read access. write a 1 to clear the bit to 0.
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 109 spi mode register the spi mode register configures the character bit width and the direction and value of the ss pin. reserved these bits are reserved and must be 0. numbits[2:0]?number of data b its per character to transfer this field contains the number of bits to shift for each char acter transfer. refer to the spi data register description for information on valid bit positio ns when the character length is less than 8-bits. 000 = 8 bits 001 = 1 bit 010 = 2 bits 011 = 3 bits 100 = 4 bits 101 = 5 bits 110 = 6 bits 111 = 7 bits. ssio?slave select i/o 0 = ss pin configured as an input. 1 = ss pin configured as an output (master mode only). ssv?slave select value if ssio = 1 and spi configured as a master: 0 = ss pin driven low (0). 1 = ss pin driven high (1). this bit has no effect if ssio = 0 or spi configured as a slave. table 63. spi mode register (spimode) bits 7 6 5 4 3 2 1 0 field reserved numbits[2:0] ssio ssv reset 000000 r/w r r/w r/w r/w r/w r/w addr f63h
ps017611-0406 serial peripheral interface z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 110 spi baud rate high and low byte registers the spi baud rate high and low byte regist ers combine to form a 16-bit reload value, brg[15:0], for the spi baud rate generator. the reload value must be greater than or equal to 0002h for proper spi operation (maximum ba ud rate is system clock frequency divided by 4). the spi baud rate is calculated using the following equation: brh = spi baud rate high byte most significant byte, brg[1 5:8], of the spi baud rate generator?s reload value. brl = spi baud rate low byte least significant byte, brg[7:0], of the spi baud rate generator?s reload value. table 64. spi baud rate high byte register (spibrh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f66h table 65. spi baud rate lo w byte register (spibrl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f67h spi baud rate (bits/s) system clock frequency (hz) 2 brg[15:0] ------------------- ---------------------- --------------------- -------------- =
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 i2c controller 111 i 2 c controller overview the i 2 c controller makes the z8f640x family device bus-compatible with the i 2 c tm pro- tocol. the i 2 c controller consists of two bidirec tional bus lines?a serial data signal (sda) and a serial clock signal (scl). features of the i 2 c controller include: ? transmit and receive operation in master mode ? maximum data rate of 400kbit/sec ? 7- and 10-bit addressing modes for slaves ? unrestricted number of data bytes transmitted per transfer the i 2 c controller in the z8f640x family de vice does not operate in slave mode. operation the i 2 c controller operates in master mode to transmit and receive data. only a single master is supported. arbitration between two masters must be accomplished in software. i 2 c supports the follo wing operations: ? master transmits to a 7-bit slave ? master transmits to a 10-bit slave ? master receives from a 7-bit slave ? master receives from a 10-bit slave sda and scl signals i 2 c sends all addresses, data and acknowledge signals over the sda line, most-significant bit first. scl is the common clock for the i 2 c controller. when the sda and scl pin alternate functions are selected for their respective gpio port s, the pins are automatically configured for open -drain operation. the master (i 2 c) is responsible for driving the scl clock signal, although the clock signal can become skewed by a slow slave device. du ring the high period of the clock, the slave pulls the scl signal low to suspend the tran saction. when the slave has released the line, the i 2 c controller continues the transaction. all data is transferred in bytes and there is no
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 112 limit to the amount of data transferred in one operation. when transmitting data or acknowledging read data from the slave, the s da signal changes in the middle of the low period of scl and is sampled in the middle of the high period of scl. i 2 c interrupts the i 2 c controller contains three sources of interrupts?transmit, receive and not acknowledge (nak) interrupts. nak interrupts oc cur when a not acknowledge is received from the slave or sent by the i 2 c controller and the start or stop bit is set. this source sets bit 0 and can only be cleared by se tting the start or stop bit. when this inter- rupt occurs, the i 2 c controller waits until it is cleared before performing an y action. in an interrupt service routine, this interrupt must be the first thing polled. receive interrupts occur when a byte of data has been received by the i 2 c master. this interrupt is cleared by reading from the i 2 c data register. if no action is taken, the i 2 c controller waits until this interrupt is cleared before performing any other action. for transmit interrupts to occur, the txi bit must be 1 in the i 2 c control register. trans- mit interrupts occur un der the following cond itions when the transmit data register is empty: ? the i 2 c controller is idle (not performing an operation). ? the start bit is set and there is no valid data in the i 2 c shift or i 2 c data register to shift out. ? the first bit of the byte of an address is shifting out and the rd bit of the i 2 c status register is deasserted. ? the first bit of a 10-bit address shifts out. ? the first bit of write data shifted out. writing to the i 2 c data register always clears a transmit interrupt. start and stop conditions the master (i 2 c) drives all start and stop signals an d initiates all transactions. to start a transaction, the i 2 c controller generates a start condition by pu lling the sda signal low while scl is high. then a high-to-low tr ansition occurs on the sda signal while the clock is high. to comple te a transaction, the i 2 c controller generates a stop condition by creating a low-to-high transition of the sda signal in the middle of the high period of the scl signal.when the scl signal is high, th e master generates a start bit by pulling a high sda signal low and generates a stop bit by releasing the sda signal. the start and stop signals are found in the i 2 c control register and must be written by software when the z8f640x family device must begin or end a transaction. writing a transaction wi th a 7-bit address 1. the i 2 c controller shifts the i 2 c shift register out onto sda signal. note:
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 113 2. the i 2 c controller waits for the slave to sen d an acknowledge (by pulling the sda signal low). if the slave pulls the sda signal high (not-acknowledge), the i 2 c controller sends a stop signal. 3. if the slave needs to service an interrupt, it pulls the sc l signal low, which halts i 2 c operation. 4. if there is no other data in the i 2 c data register or the stop bit in the i 2 c control register is set by software, then the stop signal is sent. figure 79 illustrates the data transfer format for a 7-bit addressed slave. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 79. 7-bit addressed slave data transfer format the data transfer format for a transmit opera tion on a 7-bit addressed slave is as follows: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts, because the i 2 c data register is empty 4. software responds to the tdre bit by writing a 7-bit slave address followed by a 0 (write) to the i 2 c data register. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address has been shifted ou t by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the co ntents of the data into the i 2 c data register. 10. the i 2 c controller shifts the rest of the ad dress and write bit out by the sda signal. 11. the i 2 c slave sends an acknowledge (by pulling the sda signal low) during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. 12. the i 2 c controller loads the contents of the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the data out of via th e sda signal. after the first bit is sent, the transmit interrupt is asserted. a a data a data p s a/a slave address w=0 data
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 114 14. software responds by setting the stop bit of the i 2 c control register. 15. if no new data is to be sent or address is to be sent, software responds by clearing the txi bit of the i 2 c control register. 16. the i 2 c controller completes transmission of the data on the sda signal. 17. the i 2 c controller sends the stop condition to the i 2 c bus. writing a transaction wi th a 10-bit address 1. the i 2 c controller shifts the i 2 c shift register out onto sda signal. 2. the i 2 c controller waits for the slave to sen d an acknowledge (by pulling the sda signal low). if the slave pulls the sda signal high (not-acknowledge), the i 2 c controller sends a stop signal. 3. if the slave needs to service an interrupt, it pulls the scl signal low, which halts i 2 c operation. 4. if there is no other data in the i 2 c data register or the stop bit in the i 2 c control register is set by software, then the stop signal is sent. the data transfer format for a 10-bit addressed slave is illustrated in the figure below. shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 80. 10-bit addressed slave data transfer format the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the write signal. the transmit operatio n is carried out in the same manner as 7-bit addressing. the data transfer format for a transmit opera tion on a 10-bit addressed slave is as follows: 1. software asserts the ien bit in the i 2 c control register. 2. software asserts the txi bit of the i 2 c control register to enable transmit interrupts. 3. the i 2 c interrupt asserts because the i 2 c data register is empty. 4. software responds to the tdre bit by writing the first sl ave address byte. the least- significant bit must be 0 for the write operation. 5. software asserts the start bit of the i 2 c control register. 6. the i 2 c controller sends the start condition to the i 2 c slave. a a data a data p slave address 2nd byte s a/a slave address 1st 7 bits w=0
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 115 7. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 8. after one bit of address is shifted out by the sda signal, the transmit interrupt is asserted. 9. software responds by writing the second byte of address in to the contents of the i 2 c data register. 10. the i 2 c controller shifts the rest of the first byte of address and write bit out by the sda signal. 11. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. 12. the i 2 c controller loads the contents of the i 2 c shift register with the contents of the i 2 c data register. 13. the i 2 c controller shifts the data out by the sda signal. after the first bit has been sent, the transmit interrupt is asserted. 14. software responds by writing the da ta to be written out to the i 2 c control register. 15. the i 2 c controller shifts out the rest of the second byte of slave address by the sda signal. 16. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. the i 2 c controller sets the ack bit in the i 2 c status register. 17. the i 2 c controller shifts the data out by the s da signal. after the first bit is sent, the transmit interrupt is asserted. 18. software responds by asserting the stop bit of the i 2 c control register. 19. the i 2 c controller completes transmission of the data on the sda signal. 20. the i 2 c controller sends the stop condition to the i 2 c bus. reading a transaction with a 7-bit address figure 81 illustrates the data transfer format for a receive operation on a 7-bit addressed slave. the shaded regions indica te data transferred from the i 2 c controller to slaves and unshaded regions indicate data tr ansferred from the slaves to the i 2 c controller. figure 81. receive data transfer format for a 7-bit addressed slave the data transfer format for a receive operat ion on a 7-bit addressed slave is as follows: s slave address r=1 a data a data a p
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 116 1. software writes the i 2 c data register with a 7-bit slave address followed by a 1 (read). 2. software asserts the start bit of the i 2 c control register. 3. software asserts the nak bit of the i 2 c control register so that after the first byte of data has been read by the i 2 c controller, a not acknowledge is sent to the i 2 c slave. 4. the i 2 c controller sends the start condition. 5. the i 2 c controller sends the address and read bit by the sda signal. 6. the i 2 c slave sends an acknowledge by pulli ng the sda signal low during the next high period of scl. 7. the i 2 c controller reads the first byte of data from the i 2 c slave. 8. the i 2 c controller asserts the receive interrupt. 9. software responds by reading the i 2 c data register. 10. the i 2 c controller sends a nak to the i 2 c slave. 11. a nak interrupt is generated by the i 2 c controller. 12. software responds by setting the stop bit of the i 2 c control register. 13. a stop condition is sent to the i 2 c slave. reading a transaction wi th a 10-bit address figure 82 illustrates the receive format for a 10-bit addressed slave. the shaded regions indicate data transferred from the i 2 c controller to slaves and unshaded regions indicate data transferred from the slaves to the i 2 c controller. figure 82. receive data format for a 10-bit addressed slave the first seven bits transmi tted in the first byte are 11110xx . the two bits xx are the two most-significant bits of the 10-bit address. the lowest bit of the first byte transferred is the write signal. the data transfer format for a receive operat ion on a 10-bit addressed slave is as follows: 1. software writes an address 11110b followed by the two address bits and a 0 (write). 2. software asserts the start bit of the i 2 c control register. 3. the i 2 c controller sends the start condition. s slave address 1st 7 bits w=0 a slave address 2nd byte a s slave address 1st 7 bits r=1 a data adata a p
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 117 4. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 5. after the first bit has been shifted out, a transmit interrupt is asserted. 6. software responds by writing ei ght bits of address to the i 2 c data register. 7. the i 2 c controller completes shifting of th e two address bits and a 0 (write). 8. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. 9. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 10. the i 2 c controller shifts out the next eight bits of address. after the first bits are shifted, the i 2 c controller generates a transmit interrupt. 11. software responds by setting the start bit of the i 2 c control register to generate a repeated start. 12. software responds by writing 11110b followed by the 2-bit slave address and a 1 (read). 13. software responds by setting the nak bit of the i 2 c control register, so that a not acknowledge is sent after the first byte of data has been read. if you want to read only one byte, software responds by setting the nak bit of the i 2 c control register. 14. after the i 2 c controller shifts out the address bits mentioned in step 9, the i 2 c slave sends an acknowledge by pulling the sda sign al low during the next high period of scl. 15. the i 2 c controller sends the re peated start condition. 16. the i 2 c controller loads the i 2 c shift register with the contents of the i 2 c data register. 17. the i 2 c controller sends 11110b followed by the 2-bit slave read and a 1 (read). 18. the i 2 c slave sends an acknowledge by pulling the sda signal low during the next high period of scl. 19. the i 2 c slave sends a byte of data. 20. a receive interrupt is generated. 21. software responds by reading the i 2 c data register. 22. software responds by setting the stop bit of the i 2 c control register. 23. a nak condition is sent to the i 2 c slave. 24. a stop condition is sent to the i 2 c slave.
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 118 i 2 c control register definitions i 2 c data register the i 2 c data register holds the data th at is to be loaded into the i 2 c shift register during a write to a slave. this register also holds data that is loaded from the i 2 c shift register dur- ing a read from a slave. the i 2 c shift is not accessible in the register file address space, but is used only to buffer incoming and outgoing data. i 2 c status register the read-only i 2 c status register indicates the status of the i 2 c controller. tdre?transmit data register empty when the i 2 c controller is enabled, this bit is 1 when the i 2 c data register is empty. when active, this bit causes the i 2 c controller to generate an interrupt, except when the i 2 c controller is shifting in data during the r eception of a byte or when shifting an address and the rd bit is set. this bit and the interru pt are cleared by writing to the i 2 cd register. rdrf?receive data register full this bit is set active high when the i 2 c controller is enabled and the i 2 c controller has table 66. i 2 c data register (i2cdata) bits 7 6 5 4 3 2 1 0 field data reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f50h table 67. i 2 c status register (i2cstat) bits 7 6 5 4 3 2 1 0 field tdre rdrf ack 10b rd tas dss ncki reset 10000000 r/w rrrrrrrr addr f51h
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 119 received a byte of data. when active, this bit causes the i 2 c controller to generate an interrupt. this bit is cleared by reading the i 2 c data register. ack?acknowledge this bit indicates the st atus of the acknowledge for the last byte transmitted or received. when set, this bit indicates th at an acknowledge was received for the last byte transmitted or received. 10b?10-bit address this bit indicates whether a 10- or 7-b it address is being transmitted. after the start bit is set, if the five most-significant bits of the address are 11110b , this bit is set. when set, it is reset once the first byte of the address has been sent. rd?read this bit indicates the direction of transfer of the data. it is active hi gh during a read. the status of this bit is determined by the least-significant bit of the i 2 c shift register after the start bit is set. tas?transmit address state this bit is active high while the ad dress is being shifted out of the i 2 c shift register. dss?data shift state this bit is active high while data is being transmitted to or from the i 2 c shift register. ncki?nack interrupt this bit is set high when a not acknowledge condition is rece ived or sent and neither the start nor the stop bit is active. when set, th is bit generates an interrupt that can only be cleared by setting the start or stop bit, allowing the user to specify whether he wants to perform a stop or a repeated start . i 2 c control register the i 2 c control register enables the i 2 c operation. ien?i 2 c enable this bit enables the i 2 c transmitter and receiver. table 68. i 2 c control register (i2cctl) bits 7 6 5 4 3 2 1 0 field ien start stop birq txi nak flush filten reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f52h
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 120 start?send start condition this bit sends the start condition. on ce asserted, it is cleared by the i 2 c controller after it sends the start condition or by deasserting the ien bit. after this bit is set, the start condition is sent if there is data in the i 2 c data or i 2 c shift register. if there is no data in one of these registers, the i 2 c controller waits until data is lo aded. if this bit is set while the i 2 c controller is shifting out data, it generates a start condition after the byte shifts and the acknowledge ph ase completed. if the stop bit is also set, it also waits until the stop condition is sent before the start condition. if this bit is 1, it cannot be cleared to 0 by writing to the register.this bit clears when the i 2 c is disabled. stop?send stop condition this bit causes the i 2 c controller to issue a stop co ndition after the byte in the i 2 c shift register has completed transmission or after a byte has been received in a receive opera- tion. once set, this bit is reset by the i 2 c controller after a stop co ndition has been sent or by deasserting the ien bit. if this bit is 1, it cannot be cleared to 0 by writing to the regis- ter.this bit clears when the i 2 c is disabled. birq?baud rate genera tor interrupt request this bit causes an interrupt to occur every tim e the baud rate genera tor counts down to zero. this bit allows the i 2 c controller to be used as an additional counter when it is not being used elsewhere. this bit must only be set when the i 2 c controller is disabled. txi?enable tdre interrupts this bit enables interrupts when the i 2 c data register is empty on the i 2 c controller. nak?send nak this bit sends a not acknowledge condition after the next byte of data has been read from the i 2 c slave. once asserted, it is deasserted after a not acknowledge is sent or the ien bit is deasserted. flush?flush data setting this bit to 1 clears the i 2 c data register and sets the tdre bit to 1. this bit allows flushing of the i 2 c data register when an nak is rece ived after the data has been sent to the i 2 c data register. reading th is bit always returns 0. filten?i 2 c signal filter enable setting this bit to 1 enables low-pass digita l filters on the sda and scl input signals. these filters reject any input pulse with period s less than a full system clock cycle. the fil- ters introduce a 3-system cloc k cycle latency on the inputs.
ps017611-0406 i2c controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 121 i 2 c baud rate high and low byte registers the i 2 c baud rate high and low byte registers combine to form a 16 -bit reload value, brg[15:0], for the i 2 c baud rate generator. the i 2 c baud rate is calculated using the fol- lowing equation: . brh = i 2 c baud rate high byte most significant byte , brg[15:8], of the i 2 c baud rate generator?s reload value. brl = i 2 c baud rate low byte least significant byte, brg[7:0], of the i 2 c baud rate generator?s reload value. table 69. i 2 c baud rate high byte register (i2cbrh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f53h table 70. i 2 c baud rate low by te register (i2cbrl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f54h i2c baud rate (bits/s) system clock frequency (hz) 4 brg[15:0] ------------------- --------------------- --------------------- --------------- =
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 direct memory access controller 122 direct memory access controller overview the z8f640x family device?s direct memory access (dma) controller provides three independent direct memory access channels . two of the channels (dma0 and dma1) transfer data between the on-chip peripheral s and the register file. the third channel (dma_adc) controls the anal og-to-digital converter (adc) operation and transfers the single-shot mode adc output data to the register file. operation dma0 and dma1 operation dma0 and dma1, referred to collectively as dma x , transfer data either from the on-chip peripheral control registers to the register f ile, or from the register file to the on-chip peripheral control regi sters. the sequence of operations in a dma x data transfer is: 1. dma x trigger source requests a dma data transfer. 2. dma x requests control of the system bus (address and data) from the ez8 cpu. 3. after the ez8 cpu acknowled ges the bus request, dma x transfers either a single byte or a two-byte word (depending upon conf iguration) and then returns system bus control back to the ez8 cpu. 4. if current address equals end address: ?dma x reloads the original start address ? if configured to generate an interrupt, dma x sends an interrupt request to the interrupt controller ? if configured for single-pass operation, dma x resets the den bit in the dma x control register to 0 and the dma is disabled. if current address does not equal end addr ess, the current address increments by 1 (single-byte transfer) or 2 (two-byte word transfer).
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 123 configuring dma0 and dma1 for data transfer follow these steps to configur e and enable dma0 or dma1: 1. write to the dma x i/o address register to set the re gister file address identifying the on-chip peripheral control register. the uppe r nibble of the 12-bit address for on-chip peripheral control registers is always fh . the full address is {fh, dma x _io[7:0]} 2. determine the 12-bit start and end register file addresses. the 12-bit start address is given by {dma x _h[3:0], dma_start[7:0]}. the 12-bit end address is given by {dma x _h[7:4], dma_end[7:0]}. 3. write the start and end register f ile address high nibbles to the dma x end/start address high nibble register. 4. write the lower byte of the start address to the dma x start/current address register. 5. write the lower byte of the end address to the dma x end address register. 6. write to the dma x control register to complete the following: ? select loop or single-pass mode operation ? select the data transfer direction (eithe r from the register file ram to the on- chip peripheral control register; or from the on-chip peripheral control register to the register file ram) ? enable the dma x interrupt request, if desired ? select word or byte mode ? select the dma x request trigger ? enable the dma x channel dma_adc operation dma_adc transfers data from the adc to the register file. the sequence of operations in a dma_adc data transfer is: 1. adc completes conversion on the current adc input channel and signals the dma controller that two-bytes of ad c data are ready for transfer. 2. dma_adc requests control of the system bus (address and data) from the ez8 cpu. 3. after the ez8 cpu acknowledges the bus request, dma_adc transfers the two-byte adc output value to the register file and th en returns system bus control back to the ez8 cpu. 4. if the current adc analog input is the highest numbered input to be converted: ? dma_adc resets the adc analog input nu mber to 0 and initiates data conversion on adc analog input 0. ? if configured to generate an interrupt, dma_adc sends an interrupt request to the interrupt controller
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 124 if the current adc analog input is not the highest numbered input to be converted, dma_adc initiates data conversion in the next higher numbered adc analog input. configuring dma_adc for data transfer follow these steps to conf igure and enable dma_adc: 1. write the dma_adc address register with th e 7 most-significant bits of the register file address for data transfers. 2. write to the dma_adc control regi ster to complete the following: ? enable the dma_adc interrupt request, if desired ? select the number of adc analog inputs to convert ? enable the dma_adc channel when using the dma_adc to perform conversions on multiple adc in- puts and the adc_in field in the dma_adc control register is greater than 000b, the analog-to-digital conver ter must be configured for single- shot mode. continuous mode operation of the adc can only be used in conjunction with dma_adc if the adc_in field in the dma_ adc control register is reset to 000b to enable conv ersion on adc analog input 0 only. dma control register definitions dma x control register the dma x control register is used to enable a nd select the mode of operation for dma x . den?dma x enable 0 = dma x is disabled and data transfer requests are disregarded. table 71. dma x control register (dma x ctl) bits 7 6 5 4 3 2 1 0 field den dle ddir irqen wsel rss reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fb0h, fb8h caution:
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 125 1 = dma x is enabled and initiates a data transfer upon receipt of a request from the trigger source. dle?dma x loop enable 0 = dma x reloads the original start address and is then disabled after the end address data is transferred. 1 = dma x , after the end address data is transfe rred, reloads the original start address and continues operating. ddir?dma x data transfer direction 0 = register file on-chip peripheral control register. 1 = on-chip peripheral control register register file. irqen?dma x interrupt enable 0 = dma x does not generate any interrupts. 1 = dma x generates an interrupt when the end address data is transferred. wsel?word select 0 = dma x transfers a single byte per request. 1 = dma x transfers a two-byte word per request. the address for the on-chip peripheral control register must be an even address. rss?request trigger source select the request trigger source select field determ ines the peripheral that can initiate a dma request transfer. the corresponding interrupts do not need to be enab led within the inter- rupt controller to initiate a dma transfer. ho wever, if the request trigger source can enable or disable the interrupt request sent to the interrupt controller, the interrupt request must be enabled within the re quest trigger source block. 000 = timer 0. 001 = timer 1. 010 = timer 2. 011 = timer 3. 100 = dma0 control register: uart0 received data register contains valid data. dma1 control register: uart0 transmit data register empty. 101 = dma0 control register: uart1 received data register contains valid data. dma1 control register: uart1 transmit data register empty. 110 = dma0 control register: i 2 c receiver interrupt. dm a1 control register: i 2 c trans- mitter interrupt register empty. 111 = reserved. dma x i/o address register the dma x i/o address register contains the low byte of the on-chip peripheral address for data transfer. the full 12-bit register file address is given by {fh, dma x _io[7:0]}.
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 126 when the dma is configured for tw o-byte word transfers, the dma x i/o address register must contain an even numbered address. dma_io?dma on-chip peripheral control register address this byte sets the low byte of the on-chip peripheral control register address on register file page fh (addresses f00h to fffh ). dma x address high nibble register the dma x address high register specifies the upper four bits of address for the start/ current and end addresses of dma x . dma_end_h?dma x end address high nibble these bits, used with the dma x end address low register, fo rm a 12-bit end address. the full 12-bit address is given by {dma_end_h[3:0], dma_end[7:0]}. dma_start_h?dma x start/current address high nibble these bits, used with the dma x start/current address low register, form a 12-bit start/ current address. the full 12-bit address is given by {dma_start_h[3:0], dma_start[7:0]}. table 72. dma x i/o address register (dma x io) bits 7 6 5 4 3 2 1 0 field dma_io reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fb1h, fb9h table 73. dma x address high nibble register (dma x h) bits 7 6 5 4 3 2 1 0 field dma_end_h dma_start_h reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fb2h, fhah
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 127 dma x start/current address low byte register the dma x start/current address low register, in conjunction with the dma x address high nibble register, forms a 12-bit start/curre nt address. writes to this register set the start address for dma operations. each time the dma completes a data transfer, the 12- bit start/current address increments by either 1 (single-byte transfer) or 2 (two-byte word transfer). reads from this regist er return the low byte of the current address to be used for the next dma data transfer.
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 128 dma_start?dma x start/current address low these bits, with the four lower bits of the dma x _h register, form the 12-bit start/current address. the full 12-bit address is given by {dma_start_h[3:0], dma_start[7:0]}. dma x end address low byte register the dma x end address low byte register, in conjunction with the dma x _h register, forms a 12-bit end address. dma_end?dma x end address low these bits, with the four upper bits of the dma x _h register, form a 12-bit address. this address is the ending location of the dma x transfer. the full 12-bit address is given by {dma_end_h[3:0], dma_end[7:0]}. dma_adc address register the dma_adc address register points to a bl ock of the register file to store adc con- version values as illustrated in table 76. this register contains the seven most-significant bits of the 12-bit register file addresses. the five least-significant bits are calculated from the adc analog input number (5 -bit base address is equal to twice the adc analog input number). the 10-bit adc conversion data is st ored as two bytes with the most significant byte of the adc data stored at the even numbered register file address. table 74. dma x start/current address low byte register (dma x start) bits 7 6 5 4 3 2 1 0 field dma_start reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fb3h, fhbh table 75. dma x end address low byte register (dma x end) bits 7 6 5 4 3 2 1 0 field dma_end reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fb4h, fbch
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 129 table 76 provides an example of the regist er file addresses if the dma_adc address register contains the value 72h. dmaa_addr?dma_adc address these bits specify the seven mo st-significant bits of the 12-bit register file addresses used for storing the adc output data. the adc analog input number defines the five least-significant bits of the register file address. full 12-bit address is {dmaa_addr[7:1], 4-bit adc analog input number, 0}. reserved this bit is reserved and must be 0. table 76. dma_adc register file address example adc analog input register file address (hex) 1 0 720h-721h 1 722h-723h 2 724h-725h 3 726h-727h 4 728h-729h 5 72ah-72bh 6 72ch-72dh 7 72eh-72fh 8 730h-731h 9 732h-733h 10 734h-735h 11 736h-737h 1 dmaa_addr set to 72h. table 77. dma_adc address register (dmaa_addr) bits 7 6 5 4 3 2 1 0 field dmaa_addr reserved reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fbdh
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 130 dma_adc control register the dma_adc control register enables and sets options (dma en able and interrupt enable) for adc operation. daen?dma_adc enable 0 = dma_adc is disabled and the adc analog input number (adc_in) is reset to 0. 1 = dma_adc is enabled. irqen?interrupt enable 0 = dma_adc does not generate any interrupts. 1 = dma_adc generates an interrupt after transferring data from the last adc analog input specified by the adc_in field. reserved these bits are reserved and must be 0. adc_in?adc analog input number these bits set the number of adc analog inputs to be used in the continuous update (data conversion followed by dma data transfer). the conversion always begins with adc analog input 0 and then progresses sequentia lly through the other selected adc analog inputs. 0000 = adc analog input 0 updated. 0001 = adc analog inputs 0-1 updated. 0010 = adc analog inputs 0-2 updated. 0011 = adc analog inputs 0-3 updated. 0100 = adc analog inputs 0-4 updated. 0101 = adc analog inputs 0-5 updated. 0110 = adc analog inputs 0-6 updated. 0111 = adc analog inputs 0-7 updated. 1000 = adc analog inputs 0-8 updated. 1001 = adc analog inputs 0-9 updated. 1010 = adc analog inputs 0-10 updated. 1011 = adc analog inputs 0-11 updated. 1100-1111 = reserved. table 78. dma_adc control register (dmaactl) bits 7 6 5 4 3 2 1 0 field daen irqen reserved adc_in reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr fbeh
ps017611-0406 direct memory access controller z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 131 dma status register the dma status register indicates the dma ch annel that generated the interrupt and the adc analog input that is currently undergoing conversion. reads from this register reset the interrupt request indicator bits ( irqa , irq1 , and irq0 ) to 0. therefore, software interrupt service routines that read this register must process all three interrupt sources from the dma. cadc[3:0]?current adc analog input this field identifies the analog input that the adc is currently converting. reserved this bit is reserved and must be 0. irqa?dma_adc interrupt request indicator this bit is automatically reset to 0 each time a read from this register occurs. 0 = dma_adc is not the source of th e interrupt from the dma controller. 1 = dma_adc completed transfer of data fro m the last adc analog input and generated an interrupt. irq1?dma1 interrupt request indicator this bit is automatically reset to 0 each time a read from this register occurs. 0 = dma1 is not the source of the interrupt from the dma controller. 1 = dma1 completed transfer of data to/from the end address and generated an interrupt. irq0?dma0 interrupt request indicator this bit is automatically reset to 0 each time a read from this register occurs. 0 = dma0 is not the source of the interrupt from the dma controller. 1 = dma0 completed transfer of data to/from the end address and generated an interrupt. table 79. dma_adc status register (dmaa_stat) bits 7 6 5 4 3 2 1 0 field cadc[3:0] reserved irqa irq1 irq0 reset 00000000 r/w rrrrrrrr addr fbfh
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 analog-to-digital converter 132 analog-to-digital converter overview the analog-to-digital converter (adc) converts an analog input signal to a 10-bit binary number. the features of the sigma-delta adc include: ? 12 analog input sources are multiple xed with general-purpose i/o ports ? interrupt upon conversion complete ? internal voltage re ference generator ? direct memory access (dma) controller can automatically initiate data conversion and transfer of the data from 1 to 12 of the analog inputs. architecture figure 83 illustrates the three major functional blocks (converter, analog multiplexer, and voltage reference generator) of the adc. the ad c converts an analog input signal to its digital representation. the 12-input analog multiplexer selects one of the 12 analog input sources. the adc requires an input reference voltage for the conversion. the voltage ref- erence for the conversion may be input thro ugh the external vref pi n or generated inter- nally by the voltage reference generator.
ps017611-0406 analog-to-digital converter z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 133 figure 83. analog-to-digital converter block diagram operation automatic power-down if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powere d-down. from this power-down state, the adc requires 40 system clock cycles to po wer-up. the adc powers up when a conver- sion is requested using the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. the steps for setting up th e adc and initiating a single-shot conversion are as follows: analog-to-digital converter ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 ana8 ana9 ana10 ana11 analog input multiplexer anain[3:0] internal voltage reference generator vref analog input reference input
ps017611-0406 analog-to-digital converter z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 134 1. enable the desired analog inputs by configuring the general-purpose i/o pins for alternate function. this configuration disa bles the digital input and output drivers. 2. write to the adc control register to co nfigure the adc and begin the conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to anain[3:0] to select one of the 12 analog input sources. ?clear cont to 0 to select a single-shot conversion. ? write to vref to enable or disable the inte rnal voltage reference generator. ?set cen to 1 to start the conversion. 3. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion. 4. when the conversion is complete, the adc control logic performs the following operations: ? 10-bit data result written to {adcd_h[7:0], adcd_l[7:6]}. ? cen resets to 0 to indicate th e conversion is complete. ? an interrupt request is sent to the interrupt controller. 5. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the sel ected analog input. each new data value over-writes the previous value stored in the adc data registers. an interrupt is generated only at the end of the first conversion after enabling. in continuous mode, users must be aware that adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its digital filter. step changes at the inpu t are not seen at the next output from the adc. the response of the adc (in all modes) is limited by the input signal bandwidth and the latency. the steps for setting up the adc and initiating continuous conversion are as follows: 1. enable the desired analog input by configuring the general-purpose i/o pins for alternate function. this disables th e digital input and output driver. 2. write to the adc control register to co nfigure the adc for continuous conversion. the bit fields in the adc control re gister may be written simultaneously: ? write to anain[3:0] to select one of the 12 analog input sources. caution:
ps017611-0406 analog-to-digital converter z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 135 ?set cont to 1 to select continuous conversion. ? write to vref to enable or disable the inte rnal voltage reference generator. ?set cen to 1 to start the conversions. 3. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the first conversion is complete. an interrupt request is not sent for subsequent conversions in continuous operation. 4. thereafter, the adc writes a new 10-bit data result to {adcd_h[7:0], adcd_l[7:6]} every 256 system clock cycles. 5. to disable continuous conversion, clear the cont bit in the adc control register to 0. dma control of the adc the direct memory access (d ma) controller can control ope ration of the adc includ- ing analog input selection and conversion en able. for more information on the dma and configuring for adc operations refer to the direct memory access controller chapter. adc control register definitions adc control register the adc control register selects the analog input channel and initiates the analog-to-dig- ital conversion. cen?conversion enable 0 = conversion is complete. writing a 0 produc es no effect. the adc automatically clears table 80. adc control register (adcctl) bits 7 6 5 4 3 2 1 0 field cen reserved vref cont anain[3:0] reset 0000 0000 r/w r/w r/w r/w r/w r/w addr f70h
ps017611-0406 analog-to-digital converter z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 136 this bit to 0 when a conversion has been completed. 1 = begin conversion. writing a 1 to this bit st arts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. reserved this bit is reserved and must be 0. vref 0 = internal voltage referen ce generator enabled. the vref pin should be left uncon- nected (or capacitively coupled to analog ground). 1 = internal voltage re ference generator disabled. an exte rnal voltage reference must be provided through the vref pin. cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles. 1 = continuous conversion. adc data updated every 256 system clock cycles. anain?analog input select these bits select the analog inpu t for conversion. not all port pins in this list are available in all packages for the z8f640x fa mily of products. refer to the signal and pin descrip- tions chapter for information regarding the port pins available with each package style. do not enable unavailable analog inputs. 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 0101 = ana5 0110 = ana6 0111 = ana7 1000 = ana8 1001 = ana9 1010 = ana10 1011 = ana11 11xx = reserved.
ps017611-0406 analog-to-digital converter z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 137 adc data high byte register the adc data high byte register contains th e upper eight bits of the 10-bit adc output. during a conversion, this value is invalid. a ccess to the adc data high byte register is read-only. the full 10-bit adc result is given by {adcd_h[7:0], adcd_l[7:6]}. adcd_h?adc data high byte this byte contains the upper eight bits of the 10-bit adc output. these bits are not valid during a conversion. these bits are undefined after a reset. adc data low bits register the adc data low bits register contains the lower two bits of the conversion value. dur- ing a conversion this value is invalid. access to the adc data low bits register is read- only. the full 10-bit adc result is gi ven by {adcd_h[7:0], adcd_l[7:6]}. adcd_l?adc data low bits these are the least significant two bits of the 10-bit adc outpu t. during a conversion, this value is invalid. these bits are undefined after a reset. reserved these bits are reserved and are always undefined. table 81. adc data high byte register (adcd_h) bits 7 6 5 4 3 2 1 0 field adcd_h reset x r/w r addr f72h table 82. adc data low bits register (adcd_l) bits 7 6 5 4 3 2 1 0 field adcd_l reserved reset xx r/w rr addr f73h
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 flash memory 138 flash memory overview the z8f640x family features up to 64kb (65,536 bytes) of non-volatile flash memory with read/write/erase capability. the flash me mory can be programmed and erased in-cir- cuit by either user code or through the on-chip debugger. the flash memory array is a rranged in pages with 512 bytes per page. the 512-byte page is the minimum flash block size that can be era sed. each page is divided into 8 rows of 64 bytes. the flash memory also contains a high sector that can be enabled for writes and erase separately from the rest of the flash array. the first 2 bytes of the flash program memory are used as op tion bits. refer to the option bits chapter for more information on their operation. table 83 describes the flash memory configuration for each device in the z8f640x fam- ily. figure 84 illustrates the flash memory arrangement. table 83. z8f640x family flash memory configurations part number flash size kb (bytes) flash pages program memory addresses flash high sector size kb (bytes) high sector addresses z8f160x 16 (16,384) 32 0000h - 3fffh 1 (1024) 3c00h - 3fffh z8f240x 24 (24,576) 48 0000h - 5fffh 2 (2048) 5800h - 5fffh z8f320x 32 (32,768) 64 0000h - 7fffh 2 (2048) 7800h - 7fffh z8f480x 48 (49,152) 96 0000h - bfffh 4 (4096) b000h - bfffh z8f640x 64 (65,536) 128 0000h - ffffh 8 (8192) e000h - ffffh
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 139 figure 84. flash memory arrangement operation the flash controller programs and erases the flash memory. the flash controller pro- vides the proper flash controls and timing fo r byte programming, page erase, and mass erase of the flash memory. the flash controlle r contains a protection mechanism, via the flash control register (fctl) to prevent a ccidental programming or erasure. the flow chart in figure 85 illustrates basic flash cont roller operation. the following subsections provide details on the various operations (lock, unlock, byte programming, page erase, and mass erase) listed in figure 85. 64kb flash program memory 0000h 128 pages 512 bytes per page 01ffh 0200h 03ffh fc00h fdffh fe00h ffffh 0400h 05ffh fa00h fbffh addresses
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 140 figure 85. flash controller operation flow chart reset unlocked. 73h no yes 8ch no yes program/erase enabled 63h no yes 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program mass erase page erase
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 141 flash operation timi ng using the flash fr equency registers before performing either a program or erase op eration on the flash memory, the user must first configure the flash frequency high an d low byte registers. the flash frequency registers allow programming and erasure of the flash with system clock frequencies rang- ing from 32khz (32768hz) through 20mhz. the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system cl ock frequency (in khz). this value is calcu- lated using the following equation:. flash programming and erasure are no t supported for system clock fre- quencies below 32khz (32768hz) or above 20mhz. the flash frequency high and low byte registers must be loaded with the correct value to in- sure proper operation of the z8f640x family device. flash code protection against external access the user code contained within the z8f640x family device?s flash memory can be pro- tected against external access via th e on-chip debugger. programming the rp option bit prevents reading of the user code thr ough the on-chip debugger. refer to the option bits chapter and the on-chip debugger chapter for more information. flash code protection against accidental program and erasure the z8f640x family device provides several le vels of protection against accidental pro- gram and erasure of the flash memory contents . this protection is pr ovided by a combina- tion of the option bits an d the locking mechanism of the flash controller. ffreq[15:0] system clock frequency (hz) 1000 --------------------- --------------------- ----------------- ----------------- = caution:
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 142 flash code protection using the option bits the fhswp and fwp option bits combine to provide th ree levels of flash program mem- ory protection as listed in table 84. refer to the option bits chapter for more informa- tion. flash code protection using the flash controller at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memo ry, unlock the flash controller by making two consecutive writes to the flash control register with the values 73h and 8ch , sequen- tially. after unlocking the flash controller, th e flash can be programmed or erased. when the flash controller is unlocked, any value wr itten to the flash control register locks the flash controller. writing the mass erase or page erase commands executes the function before locking the flash controller. byte programming when the flash controller is un locked, all writes to program memory program a byte into the flash. an erased flash byte contains all 1?s ( ffh ). the programming operation can only be used to change bits from 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of either the pa ge erase or mass erase commands. byte programming can be accomplished using the on-chip debugger's write memory command or ez8 cpu execution of the ldc or ldci instructions. refer to the ez8 cpu user manual for a description of the ldc and ld ci instructions. while the flash con- troller programs the flash memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. to exit pr ogramming mode and lock the flash, write any value to the flash control register, except the mass erase or page erase commands. table 84. flash code protect ion using the option bits fhswp fwp flash code protection description 0 0 programming and erasure disabled fo r all of flash program memory. in user code programming, pa ge erase, and mass erase are all disabled. mass erase is available through the on-chip debugger. 1 0 programming and page erase are enable d for the high sector of the flash program memory only. the high sector on the z8f640x family device contains 1kb to 4kb of flash with a ddresses at the top of the available flash memory. programming and page erase are disabled for the other portions of the flash program memory . mass erase through user code is disabled. mass erase is available through the on-chip debugger. 0 or 1 1 programming, page erase, and ma ss erase are enabled for all of flash program memory.
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 143 the byte at each address of the flas h memory cannot be programmed (any bits written to 0) more than twi ce before an era se cycle occurs. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh. the flash page select register identi- fies the page to be erased. with the fl ash controller unlocked, writing the value 95h to the flash control register initiates the page er ase operation. while th e flash controller exe- cutes the page erase operation, the ez8 cp u idles but the system clock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. if the page erase operation is performed through the on-chip debugger, poll the flash status register to determine when the page erase operation is complete. when the page erase is complete, the flash controller re turns to its locked state. mass erase the flash memory can also be mass erased using the flash controller. mass erasing the flash memory sets all bytes to the value ffh . with the flash controller unlocked, writing the value 63h to the flash control register initia tes the mass erase operation. while the flash controller executes the mass erase oper ation, the ez8 cpu idles but the system clock and on-chip peripherals continue to op erate. typically, the flash memory is mass erased using the on-chip debugger. via the on-chip debugger, poll the flash status reg- ister to determine when the mass erase operat ion is complete. althou gh the flash can be mass erased by user program code, when th e mass erase is complete the user program code is completely erased. wh en the mass erase is complete, the flash controller returns to its locked state. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster row program- ming algorithms by controlling the flash programming signals directly. row programing is recommended for gang programming applications and large volume customers who do not require in-circuit in itial programming of the flash memory. mass erase and page erase operations are also su pported when the flash controller is bypassed. please refer to the document entitled third-party flash programming support for z8 encore!? for more information on bypassing the flash controller. this document is available for download at www.zilog.com . caution:
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 144 flash control register definitions flash control register the flash controller must be unlocked via the flash control register before programming or erasing the flash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the fl ash controller. when the flas h controller is unlocked, writ- ing to the flash control register can initiate e ither page erase or mass erase of the flash memory. writing an invalid value or an invalid sequence returns the flash controller to its locked state. the write-only flash control regi ster shares its register file address with the read-only flash status register. fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command (must be third comm and in sequence to in itiate page erase). 63h = mass erase command (must be third comm and in sequence to initiate mass erase). table 85. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww addr ff8h
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 145 flash status register the flash status register indicates the current state of the flash controller. this register can be read at any time. the read-only flash status register shares its register file address with the write-only flash control register. reserved these bits are reserved and must be 0. fstat?flash controller status 000000 = flash controller locked. 000001 = first unlock command received. 000010 = flash controller unlocked (second unlock command received). 001xxx = program operation in progress. 010xxx = page erase operation in progress. 100xxx = mass erase operation in progress. table 86. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr addr ff8h
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 146 flash page select register the flash page select register is used to select one of the 128 available flash memory pages to be erased in a page erase operation. each flash page contains 512 bytes of flash memory. during a page erase operation, all fl ash memory having addresses with the most significant 7-bits given by fps[6:0] are erased (all bytes written to ffh ). reserved this bit is reserved and must be 0. page?page select this 7-bit field identifies the flash me mory page for page erase operation. program memory address[15:9] = page[6:0] table 87. flash page se lect register (fps) bits 7 6 5 4 3 2 1 0 field reserved page reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ff9h
ps017611-0406 flash memory z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 147 flash frequency high a nd low byte registers the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq, to control timing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated using the following equation:. flash programming and erasure is not supported for system clock frequen- cies below 32khz (32768hz) or ab ove 20mhz. the flash frequency high and low byte registers must be loaded with the correct value to in- sure proper operation of the z8f640x family device. ffreqh?flash frequency high byte high byte of the 16-bit flash frequency value. ffreql?flash frequency low byte low byte of the 16-bit flash frequency value. table 88. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ffah table 89. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr ffbh ffreq[15:0] ffreqh[7:0],ffreql[7:0] {} system clock frequency 1000 ---------------- ------------------ ------------------ ----------- == caution:
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 option bits 148 option bits overview option bits allow user configuration of certain aspects of z8f640x family device opera- tion. the feature configuration data is stor ed in the program memory and read during reset. the features available for control via the option bits are: ? watch-dog timer time-out response sel ection?interrupt or short reset. ? watch-dog timer enabled at reset. ? the ability to prevent unwant ed read access to user code in program memory. ? the ability to prevent accident al programming and erasure of all or a portion of the user code in program memory. operation option bit configuration by reset each time the option bits are programmed or er ased, the z8f640x family device must be reset for the change to take place. during any reset operation (system reset, short reset, or stop mode recovery), the option bits are automatically read from the program mem- ory and written to option configuration regist ers. the option configuration registers con- trol operation of the z8f640x family device. option bit control of the z8f640x family device is established before the device ex its reset and the ez8 cpu begins code execu- tion. the option configuration registers are not part of the register file and are not acces- sible for read or write access. option bit address space the first two bytes of program memory at addresses 0000h and 0001h are reserved for the user option bits. the byte at program memory address 0000h is used to configure user options. the byte at program memory address 0001h is reserved for future use and must be left in its unprogrammed state.
ps017611-0406 option bits z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 149 program memory address 0000h wdt_res?watch-dog timer reset 0 = watch-dog timer time-out generates an inte rrupt request. interrupts must be globally enabled for the ez8 cpu to ackno wledge the interrupt request. 1 = watch-dog timer time-out causes a short re set. this setting is the default for unpro- grammed (erased) flash. wdt_ao?watch-dog timer always on 0 = watch-dog timer is automatically enable d upon application of system power. watch- dog timer can not be disabled. 1 = watch-dog timer is enabled upon executi on of the wdt instruction. once enabled, the watch-dog timer can only be disabled by a reset or stop mode recovery. this set- ting is the default for un programmed (erased) flash. reserved these option bits are reserved for future use an d must always be set to 1. this setting is the default for unprogrammed (erased) flash. rp?read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for un programmed (erased) flash. table 90. option bits at program memory address 0000h bits 7 6 5 4 3 2 1 0 field wdt_res wdt_ao reserved rp fhswp fwp reset uuuuuuuu r/w r/w r/w r/w r/w r/w r/w r/w r/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps017611-0406 option bits z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 150 fhswp ?flash high sector write protect fwp ?flash write protect these two option bits combine to provide 3 levels of program memory protection: program memory address 0001h reserved these option bits are reserved for future use and must always be 1. this setting is the default for unprogram med (erased) flash. fhswp fwp description 0 0 programming and erasure disabled for all of program memory. programming, page erase, and mass eras e via user code is disabled. mass erase is available through the on-chip debugger. 1 0 programming and page erase are en abled for the high sector of the program memory only. the high sector on the z8f640x family device contains 1kb to 4kb of flash with a ddresses at the top of the available flash memory. programming and page erase are disabled for the other portions of the program memory. mass erase through user code is disabled. mass erase is available through the on-chip debugger. 0 or 1 1 programming, page erase, and mass erase are enabled for all of program memory. table 91. options bits at program memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/w r/w r/w r/w r/w r/w r/w r/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write.
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 on-chip debugger 151 on-chip debugger overview the z8f640x family devices have an integr ated on-chip debugger (ocd) that provides advanced debugging features including: ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints and watchpoints ? execution of ez8 cpu instructions. architecture the on-chip debugger consists of four primary functional blocks: transmitter, receiver, auto-baud generator, an d debug controller. figure 86 illust rates the architecture of the on- chip debugger figure 86. on-chip debugger block diagram auto-baud detector/generator transmitter receiver debug controller system clock dbg pin ez8 cpu control
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 152 operation ocd interface the on-chip debugger uses the dbg pin for communication with an external host. this one-pin interface is a bi-directional open-drain interface that transmits and receives data. data transmission is half-duplex, in that tr ansmit and receive cannot occur simultaneously. the serial data on the dbg pin is sent us ing the standard asynchronous data format defined in rs-232. this pin can interface the z8 f640x family device to the serial port of a host pc using minimal external hardware.t wo different methods for connecting the dbg pin to an rs-232 interface are depicted in figures 87 and 88. for operation of the on-chip debugger, all power pins (vdd and avdd) must be supplied with power, and all ground pins (vss and avss) must be properly grounded. the dbg pin is open-drain and must always be connected to v dd through an external pull-up resistor to ensure proper operation. figure 87. interfacing the on-chip debugger ?s dbg pin with an rs-232 interface (1) caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10k ohm diode
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 153 figure 88. interfacing the on-chip debugger ?s dbg pin with an rs-232 interface (2) debug mode the operating characteristics of the z8f6 40x family devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez 8 cpu, unless directed by the ocd to execute specific instructions. ? the system clock operates unless in stop mode. ? all enabled on-chip peripherals operate unless in stop mode. ? automatically exits halt mode. ? constantly refreshes the watch-dog timer, if enabled. entering debug mode the z8f640x family device enters debug mode following any of the following opera- tions: ? writing the dbgmode bit in the ocd control register to 1 using the ocd interface. ? ez8 cpu execution of a brk (breakpoint) instruction (when enabled). ? break upon a watchpoint match. ? if the dbg pin is low when the z8f640x family device exits reset, the on-chip debugger automatically puts th e device into debug mode. exiting debug mode the device exits debug mode following any of the following operations: ? clearing the dbgmode bit in the ocd control register to 0. rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10k ohm open-drain buffer
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 154 ? power-on reset ? voltage brownout reset ? asserting the reset pin low to initiate a reset. ? driving the dbg pin low while the z8f640x fa mily device is in stop mode initiates a system reset. ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (l east-significant bit first), and 1.5 stop bits (figure 89) figure 89. ocd data format ocd auto-baud detector/generator to run over a range of baud rates (data bits per second) with various system clock frequen- cies, the on-chip debugger h as an auto-baud detector/generator. after a reset, the ocd is idle until it receives data. the ocd requires th at the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits). the auto-baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocked by the z8f640x family device system clock. the minimum baud rate is the system clock frequency divided by 512. for optimal operation, the maximum recommended baud rate is the system clock frequency divided by 8. the theoretical maximum baud rate is the system clock frequency divided by 4. this theoretical maximum is possible for low noi se designs with clean signals. table 92 lists minimum and recommended maximum baud rates for sample crystal frequencies. table 92. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbits/s) minimum baud rate (kbits/s) 20.0 2500 39.1 1.0 125.0 1.96 0.032768 (32khz) 4.096 0.064 startd0d1d2d3d4d5d6d7stop
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 155 if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. th e auto-baud detector/generator can then be reconfigured by sending 80h . ocd serial errors the on-chip debugger can detect any of th e following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and ho st simultaneous transmissi on detected by the ocd) when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial brea k back to the host, and resets the auto-baud detector/generator. a framing error or tran smit collision may be caused by the host sending a serial break to the ocd. because of the open-drain natu re of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. the host should transmit a serial break on the dbg pin when first connecting to the z8f640x family device or when recovering from an error. a serial break from the host resets the auto-baud generator/detector bu t does not reset the ocd control register. a serial break leaves the z8f640x family device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial break when the dbg pin returns high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. breakpoints execution breakpoints are generated using the brk instruction (opcode 00h). when the ez8 cpu decodes a brk instruction, it signal s the on-chip debugger. if breakpoints are enabled, the ocd enters debug mode and idles the ez8 cpu. if breakpoints are not enabled, the ocd ignores the brk signal an d the brk instruction operates as an nop. breakpoints in flash memory the brk instruc tion is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the desired address, over- writing the current instruction. to remove a breakpoint, the correspon ding page of flash memory must be erased and reprogrammed with the original data. watchpoints the on-chip debugger can set one watchpoint to cause a debug break. the watchpoint identifies a single register file address. the wa tchpoint can be set to break on reads and/ or writes of the selected register file addr ess. additionally, the watc hpoint can be config- ured to break only when a specific data valu e is read and/or written from the specified reg-
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 156 ister. when the watchpoint event occurs, th e z8f640x family device enters debug mode and the dbgmode bit in the ocdctl register becomes 1. runtime counter the on-chip debugger contains a 16-bit run time counter. it counts system clock cycles between breakpoints. the counter starts co unting when the on-chip debugger leaves debug mode and stops counting when it enters debug mode again or when it reaches the maximum count of ffffh . on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation of th e z8f640x family device, only a subset of the ocd commands are available. in debug mode, all ocd commands become available unless the user code and control registers ar e protected by programming the read protect option bit ( rp ). the read protect option bit preven ts the code in memory from being read out of the z8f640x family device. when this option is enabled, several of the ocd commands are disabled. table 93 contains a summary of the on-chip debugger com- mands. each ocd command is described in further detail in the bulleted list following table 93. table 93 indicates those commands that operate when the z8f640x family device is not in debug mode (normal operatio n) and those commands that are disabled by programming the read protect option bit. table 93. on-chip debugger commands debug command command byte enabled when not in debug mode? disabled by read protect option bit read ocd revision 00h yes - reserved 01h - - read ocd status register 02h yes - read runtime counter 03h - - write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes - write program counter 06h - disabled read program counter 07h - disabled write register 08h - only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h - disabled
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 157 in the following bulleted list of ocd comman ds, data and commands sent from the host to the on-chip debugger are identified by ? dbg <-- command/data ?. data sent from the on-chip debugger back to the host is identified by ? dbg --> data ? ? read ocd revision (00h) ?the read ocd revision command is used to determine the version of the on-chip debugger. if ocd commands are added, removed, or changed, this revision number changes. dbg <-- 00h dbg --> ocdrev[15:8] (major revision number) dbg --> ocdrev[7:0] (minor revision number) ? read ocd status register (02h) ?the read ocd status register command is used to read the ocdstat register. dbg <-- 02h dbg --> ocdstat[7:0] ? read runtime counter (03h) ?the runtime counter is used to count z8 encore! system clock cycles in between breakpoint s. the 16-bit runtime counter counts up from 0000h and stops at the maximum count of ffffh . the runtime counter is overwritten during the write memory, read memory, write register, read register, read memory crc, step instruction, st uff instruction, and execute instruction commands. write program memory 0ah - disabled read program memory 0bh - disabled write data memory 0ch - yes read data memory 0dh - - read program memory crc 0eh - - reserved 0fh - - step instruction 10h - disabled stuff instruction 11h - disabled execute instruction 12h - disabled reserved 13h - 1fh - - write watchpoint 20h - disabled read watchpoint 21h - - reserved 22h - ffh - - table 93. on-chip debugger commands debug command command byte enabled when not in debug mode? disabled by read protect option bit
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 158 dbg <-- 03h dbg --> runtimecounter[15:8] dbg --> runtimecounter[7:0] ? write ocd control register (04h) ?the write ocd control register command writes the data that follows to the ocdctl register. when the read protect option bit is enabled, the dbgmode bit (ocdctl[7]) can only be set to 1, it cannot be cleared to 0 and the only method of puttin g the z8f640x family device back into normal operating mode is to reset the device. dbg <-- 04h dbg <-- ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. dbg <-- 05h dbg --> ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s progr am counter (pc). if the z8f640x family device is not in debug mode or if the read protect option bit is enabled, the program counter (pc) values are discarded. dbg <-- 06h dbg <-- programcounter[15:8] dbg <-- programcounter[7:0] ? read program counter (07h) ?the read program counter command reads the value in the ez8 cpu?s program counter (pc) . if the z8f640x family device is not in debug mode or if the read protect optio n bit is enabled, this command returns ffffh . dbg <-- 07h dbg --> programcounter[15:8] dbg --> programcounter[7:0] ? write register (08h) ?the write register command writes data to the register file. data can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). if the z8f640x family device is not in debug mode, the address and data values are discarded. if the read protect option bit is enabled, then only writes to the flash control registers are allowed and all other register write data values are discarded. dbg <-- 08h dbg <-- {4?h0,register address[11:8]} dbg <-- register address[7:0] dbg <-- size[7:0] dbg <-- 1-256 data bytes ? read register (09h) ?the read register command reads data from the register file. data can be read 1-256 bytes at a time (256 bytes can be read by setting size to
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 159 zero). if the z8f640x family device is no t in debug mode or if the read protect option bit is enabled, this command returns ffh for all the data values. dbg <-- 09h dbg <-- {4?h0,register address[11:8] dbg <-- register address[7:0] dbg <-- size[7:0] dbg --> 1-256 data bytes ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equiva lent to the ldc and ldci instructions. data can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). the on-chip flash controller mu st be written to and unlocked for the programming operation to occur. if the flas h controller is not unlocked, the data is discarded. if the z8f640x family device is not in debug mode or if the read protect option bit is enabled, the data is discarded. dbg <-- 0ah dbg <-- program memory address[15:8] dbg <-- program memory address[7:0] dbg <-- size[15:8] dbg <-- size[7:0] dbg <-- 1-65536 data bytes ? read program memory (0bh) ?the read program memo ry command reads data from program memory. this command is equivalent to the ldc and ldci instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). if the z8 f640x family device is not in debug mode or if the read protect option bit is enabled, this command returns ffh for the data. dbg <-- 0bh dbg <-- program memory address[15:8] dbg <-- program memory address[7:0] dbg <-- size[15:8] dbg <-- size[7:0] dbg --> 1-65536 data bytes ? write data memory (0ch) ?the write data memory co mmand writes data to data memory. this command is equivalent to th e lde and ldei instructions. data can be written 1-65536 bytes at a tim e (65536 bytes can be written by setting size to zero). if the z8f640x family device is not in debug mode or if th e read protect option bit is enabled, the data is discarded. dbg <-- 0ch dbg <-- data memory address[15:8] dbg <-- data memory address[7:0] dbg <-- size[15:8] dbg <-- size[7:0] dbg <-- 1-65536 data bytes
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 160 ? read data memory (0dh) ?the read data memory command reads from data memory. this command is equivalent to th e lde and ldei instructions. data can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). if the z8f640x family device is not in debug mode, this command returns ffh for the data. dbg <-- 0dh dbg <-- data memory address[15:8] dbg <-- data memory address[7:0] dbg <-- size[15:8] dbg <-- size[7:0] dbg --> 1-65536 data bytes ? read program memory crc (0eh) ?the read program memory crc command computes and returns the crc (cyclic redu ndancy check) of program memory using the 16-bit crc-ccitt polynomial. if the z8f6 40x family device is not in debug mode, this command returns ffffh for the crc value. unlike most other ocd read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and returns the result. the delay is a function of the progra m memory size and is approximately equal to the system clock period multiplied by th e number of bytes in the program memory. dbg <-- 0eh dbg --> crc[15:8] dbg --> crc[7:0] ? step instruction (10h) ?the step instruction co mmand steps one assembly instruction at the current program counte r (pc) location. if the z8f640x family device is not in debug mode or the read protect option bit is enabled, the ocd ignores this command. dbg <-- 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly instruction and allows specification of the fi rst byte of the instruction. the remaining 0-4 bytes of the instruction are read from program memory. this command is useful for stepping over instructions where the first byte of the in struction has been overwritten by a breakpoint. if the z8f640x family device is not in debug mode or the read protect option bit is enab led, the ocd ignores this command. dbg <-- 11h dbg <-- opcode[7:0] ? execute instruction (12h) ?the execute instruction command allows sending an entire instruction to be executed to the ez 8 cpu. this command can also step over breakpoints. the number of bytes to send for the instruction depends on the opcode. if the z8f640x family device is not in debug mode or the read protect option bit is enabled, this command reads and discards one byte. dbg <-- 12h dbg <-- 1-5 byte opcode
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 161 ? write watchpoint (20h) ?the write watchpoint command sets and configures the debug watchpoint. if the z8f640x family device is not in debug mode or the read protect option bit is enabled, the wptctl bits are all set to zero. dbg <-- 20h dbg <-- wptctl[7:0] dbg <-- wptaddr[7:0] dbg <-- wptdata[7:0] ? read watchpoint (21h) ?the read watchpoint command reads the current watchpoint registers. dbg <-- 21h dbg --> wptctl[7:0] dbg --> wptaddr[7:0] dbg --> wptdata[7:0] on-chip debugger control register definitions ocd control register the ocd control register controls the state of the on-chip debugger. this register enters or exits debug mode and enables the brk inst ruction. it can also reset the z8f640x fam- ily device. a ?reset and stop? function can be achieved by writing 81h to this register. a ?reset and go? function can be achieved by writing 41h to this register. if the z8f640x family device is in debug mode, a ?run? functio n can be implemented by writing 40h to this register. dbgmode?debug mode setting this bit to 1 causes the z8f640x fam ily device to enter debug mode. when in debug mode, the ez8 cpu stops fetching new instructions. clearing this bit causes the ez8 cpu to start running again. this bit is automatically set when a brk instruction is decoded and breakpoints are enabled or when a watchpoint debug break is detected. if the read protect option bit is enabled, this bit can only be cleared by resetting the z8f640x family device, it cannot be written to 0. 0 = the z8f640x family device is operating in normal mode. 1 = the z8f640x family device is in debug mode. table 94. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 00000000 r/w r/w r/w r/w r r r r r/w
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 162 brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h). by default, break- points are disabled and the brk in struction behaves like a nop. if this bit is set to 1, when a brk instruction is decoded, the dbgmode bit of the ocdctl regi ster is automatically set to one. 0 = breakpoints are disabled. 1 = breakpoints are enabled. dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, then the ocd sends an debug acknowledge character ( ffh ) to the host when a breakpoint or watchpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. reserved these bits are reserved and must be 0. rst?reset setting this bit to 1 resets the z8f640x family device. the device goes through a normal power-on reset sequence with the exception th at the on-chip debugger is not reset. this bit is automatically cleared to 0 when the reset finishes. 0 = no effect. 1 = reset z8f640x family device. ocd status register the ocd status register reports status inform ation about the current state of the debugger and the z8f640x family device. dbg?debug status 0 = the z8f640x family device is operating in normal mode. 1 = the z8f640x family device is in debug mode. halt?halt mode 0 = the z8f640x family device is not in halt mode. 1 = the z8f640x family device is in halt mode. table 95. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field dbg halt rpen reserved reset 00000000 r/w rrrrrrrr
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 163 rpen?read protect option bit enabled 0 = the read protect option bit is disabled (1). 0 = the read protect option bit is enab led (0), disabling many ocd commands. reserved these bits are always 0. ocd watchpoint control register the ocd watchpoint control register is us ed to configure the debug watchpoint. wpw?watchpoint break on write this bit cannot be set if the re ad protect option bit is enabled. 0 = watchpoint break on register file write is disabled. 1 = watchpoint break on register file write is enabled. wpr?watchpoint break on read this bit cannot be set if the re ad protect option bit is enabled. 0 = watchpoint break on register file read is disabled. 1 = watchpoint break on register file write is enabled. wpdm?watchpoint data match if this bit is set, then the watchpoint only generates a debug break if the data being read or written matches the specified watchpoint data. either the wpr and/or wpw bits must also be set for this bit to affect operation. th is bit cannot be set if the read protect option bit is enabled. 0 = watchpoint break on read and/or write does not require a data match. 1 = watchpoint break on read and/or write requires a data match. reserved this bit is reserved and must be 0. raddr[11:8]?register address these bits specify the upper 4 bits of the re gister file address to match when generating a watchpoint debug break. the full 12-bit register file address is given by {wptctl3:0], wptaddr[7:0]}. table 96. ocd watchpoint control/address (wptctl) bits 7 6 5 4 3 2 1 0 field wpw wpr wpdm reserved wptaddr[11:8] reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w
ps017611-0406 on-chip debugger z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 164 ocd watchpoint address register the ocd watchpoint address register specifies the lower 8 bits of the register file address bus to match when generating watchpoi nt debug breaks. the full 12-bit register file address is given by {wptctl3:0], wptaddr[7:0]}. wptaddr[7:0]?watchpoint register file address these bits specify the lower eight bits of th e register address to match when generating a watchpoint debug break. ocd watchpoint data register the ocd watchpoint data register specifies the data to match if watchpoint data match is enabled. wptdata[7:0]?watchpoint register file data these bits specify the regist er file data to match when generating watchpoint debug breaks with the wpdm bit (wptctl[5]) is set to 1. ????? table 97. ocd watchpoint address (wptaddr) bits 7 6 5 4 3 2 1 0 field wptaddr[7:0] reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w table 98. ocd watchpoint data (wptdata) bits 7 6 5 4 3 2 1 0 field wptdata[7:0] reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 on-chip oscillator 165 on-chip oscillator the z8f640x family devices fe ature an on-chip oscillator fo r use with an external 1- 20mhz crystal. this oscillator generates the primary system clock for the internal ez8 cpu and the majority of the on-chip peripherals. alternatively, the x in input pin can also accept a cmos-level clock input signal (32khz -20mhz). if an external clock generator is used, the x out pin must be left unconnected. the z8f640x family device does not con- tain in internal clock divider. th e frequency of the signal on the x in input pin determines the frequency of the system clock. the z8f6 40x family device on-chip oscillator does not support external rc networks or ceramic resonators. 20mhz crystal oscillator operation figure 90 illustrates a reco mmended configuration for co nnection with an external 20mhz, fundamental-mode, pa rallel-resonant crystal. r ecommended crystal specifica- tions are provided in table 99. resistor r 1 limits total power dissip ation by the crystal. printed circuit board layout should add no more than 4pf of stray capacitance to either the x in or x out pins. if oscillation does not occur, reduce the values of capacitors c 1 and c 2 to decrease loading.
ps017611-0406 on-chip oscillator z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 166 figure 90. recommended crystal oscillat or configuration (20mhz operation) table 99. recommended crystal oscillat or specifications (20mhz operation) parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s )25 maximum load capacitance (c l ) 20 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum c2 = 22pf c1 = 22pf 20mhz crystal (fundamental-mode) r2 = 100k xout xin o n- chi p o sc ill a t or r1 = 220
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 electrical characteristics 167 electrical characteristics absolute maximum ratings stresses greater than those listed in table 100 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, unused inputs must be tied to one of the supply voltages (v dd or v ss ). table 100. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +105 c storage temperature ?65 +150 c voltage on any pin with respect to v ss ?0.3 +5.5 v 1 voltage on v dd pin with respect to v ss ?0.3 +3.6 v maximum current on input and/or inactive output pin ?5 +5 a maximum output current from active output pin -25 +25 ma 80-pin qfp maximum ratings at -40c to 70c total power dissipation 550 mw maximum current into v dd or out of v ss 150 ma 80-pin qfp maximum ratings at 70c to 105c total power dissipation 200 mw maximum current into v dd or out of v ss 56 ma 68-pin plcc maximum ratings at -40c to 70c total power dissipation 1000 mw maximum current into v dd or out of v ss 275 ma notes: 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b and port h), reset , and where noted otherwise.
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 168 68-pin plcc maximum ratings at 7 0 0 c to 105 0 c total power dissipation 500 mw maximum current into v dd or out of v ss 140 ma 64-pin lqfp maximum ratings at -40c to 70c total power dissipation 1000 mw maximum current into v dd or out of v ss 275 ma 64-pin lqfp maximum ratings at 7 0 0 c to 105 0 c total power dissipation 540 mw maximum current into v dd or out of v ss 150 ma 44-pin plcc maximum ratings at -40c to 70c total power dissipation 750 mw maximum current into v dd or out of v ss 200 ma 44-pin plcc maximum ratings at 7 0 0 c to 105 0 c total power dissipation 295 mw maximum current into v dd or out of v ss 83 ma 44-pin lqfp maximum ratings at -40c to 70c total power dissipation 750 mw maximum current into v dd or out of v ss 200 ma 44-pin lqfp maximum ratings at 7 0 0 c to 105 0 c total power dissipation 410 mw maximum current into v dd or out of v ss 114 ma 40-pin pdip maximum ratings at -40c to 70c total power dissipation 1000 mw maximum current into v dd or out of v ss 275 ma 40-pin pdip maximum ratings at 70c to 105c total power dissipation 540 mw maximum current into v dd or out of v ss 150 ma table 100. absolute maximum ratings parameter minimum maximum units notes notes: 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b and port h), reset , and where noted otherwise.
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 169 dc characteristics table 101 lists the dc characteristics of the z8f640x family devices. all voltages are ref- erenced to v ss , the primary system ground. table 101. dc characteristics symbol parameter t a = -40 0 c to 105 0 c units conditions minimum typical maximum v dd supply voltage 3.0 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v for all input pins except reset , dbg, and xin. v il2 low level input voltage -0.3 ? 0.2*v dd v for reset , dbg, and xin. v ih1 high level input voltage 0.7*v dd ? 5.5 v port a, c, d, e, f, and g pins. v ih2 high level input voltage 0.7*v dd ? v dd +0.3 v port b and h pins. v ih3 high level input voltage 0.8*v dd ? v dd +0.3 v reset , dbg, and xin pins. v ol1 low level output voltage ? ? 0.4 v v dd = 3.0v; i ol = 2ma high output drive disabled. v oh1 high level output voltage 2.4 ?? v v dd = 3.0v; i oh = -2ma high output drive disabled. v ol2 low level output voltage ? ? 0.6 v v dd = 3.3v; i ol = 20ma high output drive enabled. t a = -40 0 c to +70 0 c v ol3 low level output voltage ? ? 0.6 v v dd = 3.3v; i ol = 15ma high output drive enabled. t a = 70 0 c to +105 0 c v oh2 high level output voltage 2.4 ?? v v dd = 3.3v; i oh = -20ma high output drive enabled. t a = -40 0 c to +70 0 c v oh3 high level output voltage 2.4 ?? v v dd = 3.3v; i oh = -15ma high output drive enabled. t a = 70 0 c to +105 0 c i il input leakage current -5 ? +5 a v dd = 3.6v; v in = vdd or vss 1 i tl tri-state leakage current -5 ? +5 a v dd = 3.6v c pad gpio port pad capacitance ? 8.0 2 ? pf c xin xin pad capacitance ? 8.0 2 ? pf c xout xout pad capacitance ? 9.5 2 ? pf
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 170 figure 91 illustrates the typical current consumption while oper ating at 25oc, 3.3v, versus the system clock frequency. stics i pu weak pull-up current 30 100 350 a v dd = 3.0 - 3.6v i ccs supply current in stop mode 600 a v dd = 3.3v 1 this condition excludes all pins that have on-chip pull-ups, when driven low. 2 these values are provided for design guid ance only and are not tested in production. figure 91. nominal icc versus system clock frequency table 101. dc characteristics symbol parameter t a = -40 0 c to 105 0 c units conditions minimum typical maximum 0.0 10.0 20.0 30 . 0 0 5 10 15 20 frequency (mhz) icc (ma)
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 171 figure 92 illustrates the typical current co nsumption in halt mode while operating at 25oc, 3.3v, versus the system clock frequency. figure 92. nominal halt mode i cc versus system clock frequency 0.000 5.000 10.000 15.000 0 5 10 15 20 frequency (mhz) icc in halt mode (ma)
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 172 ac characteristics the section provides information on the ac characteristics and timing of the z8 encore!?. all ac timing information assumes a standard load of 50pf on all outputs. table 102. ac characteristics symbol parameter v dd = 3.0 - 3.6v t a =-40 0 c to 105 0 c units conditions minimum maximum f sysclk system clock frequency ? 20.0 mhz read-only from flash memory. 0.032768 20.0 mhz program or erasure of the flash memory. f xtal crystal oscillator frequency 1.0 20.0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver. t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50ns t xinl system clock low time 20 30 ns t clk = 50ns t xinr system clock rise time ? 3ns t clk = 50ns t xinf system clock fall time ? 3ns t clk = 50ns
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 173 on-chip peripheral ac and dc electrical characteristics table 103. power-on reset and voltage brow n-out electrical charac teristics and timing symbol parameter t a = -40 0 c to 105 0 c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.40 2.70 2.90 v v dd = v por v vbo voltage brown-out reset voltage threshold 2.30 2.60 2.85 v v dd = v vbo v por to v vbo hysteresis 50 100 ? mv starting v dd voltage to ensure valid power-on reset. ? v ss ? v t ana power-on reset analog delay ? 50 ? s v dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay ? 10.2 ? ms 512 wdt oscillator cycles (50khz) + 70 system clock cycles (20mhz) t vbo voltage brown-out pulse rejection period ? 10 ? ns v dd < v vbo to generate a reset. t ramp time for vdd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms 1 data in the typical column is fr om characterization at 3.3v and 0 0 c. these values are provided for design guidance only and are not tested in production. table 104. flash memory electri cal characteristics and timing parameter v dd = 3.0 - 3.6v t a = -40 0 c to 105 0 c units notes minimum typical maximum flash byte read time 50 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 174 writes to single address before next erase ?? 2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25 0 c endurance 10,000 ? ? cycles program / erase cycles table 105. watch-dog timer electrical characteristics and timing symbol parameter v dd = 3.0 - 3.6v t a = -40 0 c to 105 0 c units conditions minimum typical maximum f wdt wdt oscillator frequency 25 50 100 khz table 106. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 - 3.6v t a = -40 0 c to 105 0 c units conditions minimum typical maximum resolution ? 10 ? bits external v ref = 3.0v; r s <= 3.0 k differential nonlinearity (dnl) -1.0 ? 1.0 lsb external v ref = 3.0v; r s <= 3.0 k integral nonlinearity (inl) -3.0 ? 3.0 lsb external v ref = 3.0v; r s <= 3.0 k dc offset error -35 ? 25 mv 80-pin qfp and 64-pin lqfp packages. 1 analog source impedance affects the adc offset volta ge (because of pin leakage) and input settling time. table 104. flash memory electrical char acteristics and timing (continued) parameter v dd = 3.0 - 3.6v t a = -40 0 c to 105 0 c units notes minimum typical maximum
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 175 dc offset error -50 ? 25 mv 40-pin pdip, 44-pin lqfp, 44-pin plcc, and 68-pin plcc packages. v ref internal reference voltage ? 2.0 ? v single-shot conversion time ? 5129 ? cycles system clock cycles continuous conversion time ? 256 ? cycles system clock cycles sampling rate system clock / 256 hz signal input bandwidth ? ? 3.5 khz r s analog source impedance ? ? 10 1 k zin input impedance 150 k 20mhz system clock. input impedance increases with lower system clock frequency. v ref external reference voltage avdd v avdd <= vdd. when using an external reference voltage, decoupling capacitance should be placed from vref to avss. table 106. analog-to-digital co nverter electrical characterist ics and timing (continued) symbol parameter v dd = 3.0 - 3.6v t a = -40 0 c to 105 0 c units conditions minimum typical maximum 1 analog source impedance affects the adc offset volta ge (because of pin leakage) and input settling time.
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 176 general purpose i/o port input data sample timing figure 93 illustrates timing of the gpio port input sampling. the in put value on a gpio port pin is sampled on the rising edge of the sy stem clock. the port va lue is then available to the ez8 cpu on the second rising clock e dge following the change of the port value. figure 93. port input sample timing table 107. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to xin rise setup time (not pictured) 5? t h_port xin rise to port input transition hold time (not pictured) 5? t smr gpio port pin pulse width to insure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk port pin port value changes to 0 0 value may be read from port input input value port input data register latch clock data register
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 177 general purpose i/o port output timing figure 94 and table 108 provide timin g information for gpio port pins. figure 94. gpio port output timing table 108. gpio port output timing parameter abbreviation delay (ns) minimum maximum t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 178 on-chip debugger timing figure 95 and table 109 provide timing info rmation for dbg pins. the timing specifica- tions presume a rise and fall time on dbg of less than 4 s. figure 95. on-chip debugger timing table 109. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 10 ? t 4 dbg to xin rise input hold time 5 ? dbg frequency system clock / 4 xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 179 spi master mode timing figure 96 and table 110 provide timing information for spi master mode pins. timing is shown with sck rising edge used to source mosi output data, sck falling edge used to sample miso input data. timing on the ss output pin(s) is controlled by software. figure 96. spi master mode timing table 110. spi master mode timing parameter abbreviation delay (ns) minimum maximum t 1 sck rise to mosi output valid delay -5 +5 t 2 miso input to sck (recei ve edge) setup time 20 t 3 miso input to sck (recei ve edge) hold time 0 sck mosi t1 (output) miso t2 t3 (input) output data input data
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 180 spi slave mode timing figure 97 and table 111 provide timing information for the spi slave mode pins. timing is shown with sck rising edge used to sour ce miso output data, sck falling edge used to sample mosi input data. figure 97. spi slave mode timing table 111. spi slave mode timing parameter abbreviation delay (ns) minimum maximum t 1 sck (transmit edge) to miso output valid delay 2 * xin period 3 * xin period + 20 nsec t 2 mosi input to sck (receive edge) setup time 0 t 3 mosi input to sck (receive edge) hold time 3 * xin period t 4 ss input assertion to sck setup 1 * xin period sck miso t1 (output) mosi t2 t3 (input) output data input data ss (input) t4
ps017611-0406 electrical characteristics z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 181 i 2 c timing figure 98 and table 112 provide timing information for i2c pins. figure 98. i 2 c timing table 112. i 2 c timing parameter abbreviation delay (ns) minimum maximum t 1 scl fall to sda output delay scl period/4 t 2 sda input to scl rising edge setup time 0 t 3 sda input to scl falling edge hold time 0 scl sda t1 (output) sda t2 (input) output data input data (output) t3
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 ez8 cpu instruction set 182 ez8 cpu instruction set assembly language pro gramming introduction the ez8 cpu assembly language provides a me ans for writing an application program without having to be concerned with actual memory addresses or machine instruction for- mats. a program written in assembly language is called a source program. assembly lan- guage allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to re present the instructio ns themselves. the opcodes identify the in struction while the operands represe nt memory locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called state- ments. each statement can contain labe ls, operations, operands and comments. labels can be assigned to a particular instru ction step in a source program. the label iden- tifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extended mode register address 234h , ; identifies the destination. the second operand, immediate data
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 183 ; value 01h , is the source. the value 01h is written into the ; register at address 234h . assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination? , but ordering is opcode-dependent. the fol- lowing instruction examples illust rate the format of some ba sic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. example 1 : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: example 2 : in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0 - 255 or, using escaped mode addressing, a working register r0 - r15. if the contents of register 43h and working register r8 are added and the result is stor ed in 43h, the assembl y syntax and resulting object code is: see the device-specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is described in table 115 table 113. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst) table 114. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 184 . table 116 contains additional symbols that ar e used throughout th e instruction summary and instruction set description sections. table 115. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see condition codes overview in the ez8 cpu user manual. da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. represents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0 ?15 ir indirect register @reg reg. represents a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represen ts an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15 r register reg reg. represents a numb er in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to ?128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represen ts a number in the range of 00h to ffh x indexed #index the register or register pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 185 assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is added to the destin ation data and the result is stored in the des- tination location. table 116. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 186 condition codes the c, z, s and v flags control the operatio n of the conditional jump (jp cc and jr cc) instructions. sixteen frequently useful functions of the flag settings are encoded in a 4-bit field called the condition code (cc), which form s bits 7:4 of the conditional jump instruc- tions. the condition codes are su mmarized in table 117. some binary condition codes can be created using more than one assembly code mnemonic. the result of the flag test oper- ation is used to decide if th e conditional jump is executed. table 117. condition codes binary hex assembly mnemonic definition flag test operation 0000 0 f always false ? 0001 1 lt less than (s xor v) = 1 0010 2 le less than or equal (z or (s xor v)) = 1 0011 3 ule unsigned less than or equal (c or z) = 1 0100 4 ov overflow v = 1 0101 5 ml minus s = 1 0110 6 z zero z = 1 0110 6 eq equal z = 1 0111 7 c carry c = 1 0111 7 ult unsigned less than c = 1 1000 8 t (or blank) always true ? 1001 9 ge greater than or equal (s xor v) = 0 1010 a gt greater than (z or (s xor v)) = 0 1011 b ugt unsigned greater than (c = 0 and z = 0) = 1 1100 c nov no overflow v = 0 1101 d pl plus s = 0 1110 e nz non-zero z = 0 1110 e ne not equal z = 0 1111 f nc no carry c = 0 1111 f uge unsigned greater than or equal c = 0
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 187 ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift tables 118 through 125 contain the instructions belonging to each group and the number of operands required for each instruction. some inst ructions appear in more than one table as these instruction can be considered as a subs et of more than one category. within these tables, the source operand is identified as ?s rc?, the destination op erand is ?dst? and a con- dition code is ?cc?. table 118. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 188 sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract using extended addressing table 119. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 120. block tr ansfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto-increment addresses ldei dst, src load external data to/from data memory and auto-increment addresses table 118. arithmetic in structions (continued) mnemonic operands instruction
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 189 table 121. cpu control instructions mnemonic operands instruction ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set register pointer stop ? stop mode wdt ? watch-dog timer refresh table 122. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto-increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/from data memory and auto-increment addresses ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 190 table 123. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 124. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decr ement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 191 ez8 cpu instruction summary table 126 summarizes the ez8 cpu instruc tions. the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . table 125. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 126. ez8 cpu instruction summary assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 ****0* 2 3 rir 13 24 rr 14 33 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 ****0* 4 3 er im 19 4 3 flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 192 add dst, src dst dst + src r r 02 ****0* 2 3 rir 03 24 rr 04 33 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 ****0* 4 3 er im 09 4 3 and dst, src dst dst and src r r 52 - * * 0 - - 2 3 rir 53 24 rr 54 33 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 - * * 0 - - 4 3 er im 59 4 3 bclr bit, dst dst[bit] 0re2-**0--22 bit p, bit, dst dst[bit] pre2-**0--22 brk debugger break 00 - - - - - - 1 1 bset bit, dst dst[bit] 1re2-**0--22 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 - - 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ------ 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ------ 3 3 ir f7 3 4 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 193 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ------ 3 3 ir f7 3 4 call dst sp sp -2 @sp pc pc dst irr d4 ------ 2 6 da d6 3 3 ccf c ~c ef *----- 1 2 clr dst dst 00h r b0 ------ 2 2 ir b1 2 3 com dst dst ~dst r 60 - * * 0 - - 2 2 ir 61 2 3 cp dst, src dst - src r r a2 * * * * - - 2 3 rir a3 24 rr a4 33 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 * * * * - - 3 3 rir1f a3 34 rr1f a4 43 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 * * * * - - 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 * * * * - - 4 3 er im a9 4 3 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 194 da dst dst da(dst) r 40 * * * x - - 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 - * * * - - 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 - * * * - - 2 5 irr 81 2 6 di irqctl[7] 0 8f ------ 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ------ 2 3 ei irqctl[7] 1 9f ------ 1 2 halt halt mode 7f ------ 1 2 inc dst dst dst + 1 r 20 - * * * - - 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 - * * * - - 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ****** 1 5 jp dst pc dst da 8d ------ 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ------ 3 2 jr dst pc pc + x da 8b ------ 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ------ 2 2 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 195 ld dst, rc dst src r im 0c-fc ------ 2 2 rx(r) c7 3 3 x(r) r d7 3 4 rir e3 23 rr e4 32 rir e5 3 3 rim e6 3 3 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 ldc dst, src dst src r irr c2 ------ 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 - - - - - - 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ------ 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 - - - - - - 2 9 irr ir 93 2 9 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 196 ldx dst, src dst src r er 84 ------ 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ------ 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ------ 2 8 nop no operation 0f - - - - - - 1 2 or dst, src dst dst or src r r 42 - * * 0 - - 2 3 rir 43 24 rr 44 33 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 - * * 0 - - 4 3 er im 49 4 3 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 197 pop dst dst @sp sp sp + 1 r 50 ------ 2 2 ir 51 2 3 popx dst dst @sp sp sp + 1 er d8 ------ 3 2 push src sp sp ? 1 @sp src r 70 ------ 2 2 ir 71 2 3 pushx src sp sp ? 1 @sp src er c8 ------ 3 2 rcf c 0 cf 0----- 1 2 ret pc @sp sp sp + 2 af ------ 1 4 rl dst r 90 * * * * - - 2 2 ir 91 2 3 rlc dst r 10 * * * * - - 2 2 ir 11 2 3 rr dst r e0 ****- - 2 2 ir e1 2 3 rrc dst r c0 * * * * - - 2 2 ir c1 2 3 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 198 sbc dst, src dst dst ? src - c r r 32 ****1* 2 3 rir 33 24 rr 34 33 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 ****1* 4 3 er im 39 4 3 scf c 1 df 1----- 1 2 sra dst r d0 ***0- - 2 2 ir d1 2 3 srl dst r 1f c0 **0*- - 3 2 ir 1f c1 3 3 srp src rp src im 01 ------ 2 2 stop stop mode 6f ------ 1 2 sub dst, src dst dst ? src r r 22 ****1* 2 3 rir 23 24 rr 24 33 rir 25 3 4 rim 26 3 3 ir im 27 3 4 subx dst, src dst dst ? src er er 28 ****1* 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x - - 2 2 ir f1 2 3 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 199 tcm dst, src (not dst) and src r r 62 - * * 0 - - 2 3 rir 63 24 rr 64 33 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 - * * 0 - - 4 3 er im 69 4 3 tm dst, src dst and src r r 72 - * * 0 - - 2 3 rir 73 24 rr 74 33 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 - * * 0 - - 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ------ 2 6 wdt 5f ------ 1 2 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 200 xor dst, src dst dst xor src r r b2 - * * 0 - - 2 3 rir b3 24 rr b4 33 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 - * * 0 - - 4 3 er im b9 4 3 table 126. ez8 cpu instruct ion summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a function of the result of the operation. - = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps017611-0406 ez8 cpu instruction set z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 201 flags register the flags register contains the status inform ation regarding the most recent arithmetic, logical, bit manipulation or rotate and shift oper ation. the flags register contains six bits of status information that are set or cleared by cpu operations. four of the bits (c, v, z and s) can be tested for use with conditiona l jump instructions. two flags (h and d) can- not be tested and are used for bina ry-coded decimal (bcd) arithmetic. the two remaining bits, user flags (f1 and f2 ), are available as general-purpose status bits. user flags are unaffected by arithmetic operations and must be set or cleared by instructions. the user flags cannot be used with conditional jumps. they are undefined at initial power-up and are unaffected by reset. figure 99 illustrates th e flags and their bit positions in the flags register. interrupts, the software trap (trap) instruction, and illegal instruction traps all write the value of the flags register to the stack. executing an interrupt return (iret) instruc- tion restores the value saved on th e stack into the flags register. u = undefined figure 99. flags register c z s v d h f2 f1 flags register bit 0 bit 7 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag user flags
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 opcode maps 202 opcode maps figures 101 and 102 provide information on each of the ez8 cpu in structions. a descrip- tion of the opcode map data and the abbrev iations are provided in figure 100 and table 127. figure 100. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps017611-0406 opcode maps z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 203 table 127. opcode map abbreviations abbreviation description a bbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps017611-0406 opcode maps z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 204 figure 101. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.2 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.3 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map
ps017611-0406 opcode maps z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 205 figure 102. second op code map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex)
z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? ps017611-0406 packaging 206 packaging figure 103 illustrates the 40-pin pdip (plas tic dual-inline package) available for the z8f1601, z8f2401, z8f3201, z8f4801, and z8f6401 devices. figure 103. 40-lead plastic dual-inline package (pdip)
ps017611-0406 packaging z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 207 figure 104 illustrates the 44-pin lqfp (low pr ofile quad flat package) available for the z8f1601, z8f2401, z8f3201, z8f4801, and z8f6401 devices. figure 104. 44-lead low-profile quad flat package (lqfp) figure 105 illustrates the 44-pin plcc (plastic lead chip carrier) package available for the z8f1601, z8f2401, z8f3201, z8f4801, and z8f6401 devices. figure 105. 44-lead plastic lead chip carrier package (plcc) a2 a a1 le c e he e l 0-7 b d hd detail a 0.020/0.014 0.045/0.025 0.032/0.026 r 1.14/0.64 .028/.020 0.51/0.36 0.81/0.66 d2 e e1 3. dimension : mm 2. leads are coplanar within 0.004". 1. controlling dimension : inch notes: 17 18 inch 29 28 d d1 61 7 45 40 39 a1 a 0.71/0.51 1.321/1.067 0.052/0.042 e dim. from center to center of radii d/e 0.650 0.600 d1/e1 e d2 1.27 bsc 16.51 15.24 16.00 16.66 0.050 bsc 0.630 0.656 min 0.168 0.095 0.685 symbol a1 a millimeter 4.27 2.41 17.40 min 2.92 17.65 4.57 max 0.115 0.695 0.180 inch max m
ps017611-0406 packaging z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 208 figure 105 illustrates the 64-pin lqfp (low-profile quad flat package) available for the z8f1602, z8f2402, z8f3202, z8f4802, and z8f6402 devices. figure 106. 64-lead low-profile quad flat package (lqfp) c a1 a2 a le e he e 0-7 l b hd d detail a
ps017611-0406 packaging z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 209 figure 107 illustrates the 68-pin plcc (plastic lead chip carrier) package available for the z8f1602, z8f2402, z8f3202, z8f4802, and z8f6402 devices. figure 107. 68-lead plastic lead chip carrier package (plcc)
ps017611-0406 packaging z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 210 figure 108 illustrates the 80-pin qfp (quad flat package) av ailable for the z8f4803 and z8f6403 devices. figure 108. 80-lead quad-flat package (qfp) a2 e he 1 80 b detail a 0-10 l e 24 25 detail a hd d 65 64 40 41 17.70 he 18.15 .715 .697 .004" controlling dimensions : millimeter l e e c lead coplanarity : max .10 notes: 2. 0.80 bsc 0.70 13.90 1.10 14.10 .028 .043 .0315 bsc .547 .555 a1 d hd c b a2 symbol a1 19.90 23.70 0.13 2.60 0.30 0.10 20.10 24.15 0.20 0.38 2.80 0.45 millimeter min max .783 .933 .005 .791 .951 .008 .102 .012 .004 .110 .018 .015 inch min max
ps017611-0406 ordering information z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 211 ordering information table 128. ordering information part flash kb (bytes) ram kb (bytes) max. speed (mhz) temp ( 0 c) voltage (v) package part number z8 encore! ? with 16kb flash, standard temperature z8 encore! ? 16 (16,384) 2 (2048) 20 0 to +70 3.0 - 3.6 pdip-40 z8f1601pm020sc z8 encore! ? 16 (16,384) 2 (2048) 20 0 to +70 3.0 - 3.6 lqfp-44 z8f1601an020sc z8 encore! ? 16 (16,384) 2 (2048) 20 0 to +70 3.0 - 3.6 plcc-44 z8f1601vn020sc z8 encore! ? 16 (16,384) 2 (2048) 20 0 to +70 3.0 - 3.6 lqfp-64 z8f1602ar020sc z8 encore! ? 16 (16,384) 2 (2048) 20 0 to +70 3.0 - 3.6 plcc-68 z8f1602vs020sc z8 encore! ? with 24kb flash, standard temperature z8 encore! ? 24 (24,576) 2 (2048) 20 0 to +70 3.0 - 3.6 pdip-40 z8f2401pm020sc z8 encore! ? 24 (24,576) 2 (2048) 20 0 to +70 3.0 - 3.6 lqfp-44 z8f2401an020sc z8 encore! ? 24 (24,576) 2 (2048) 20 0 to +70 3.0 - 3.6 plcc-44 z8f2401vn020sc z8 encore! ? 24 (24,576) 2 (2048) 20 0 to +70 3.0 - 3.6 lqfp-64 z8f2402ar020sc z8 encore! ? 24 (24,576) 2 (2048) 20 0 to +70 3.0 - 3.6 plcc-68 z8f2402vs020sc z8 encore! ? with 32kb flash, standard temperature z8 encore! ? 32 (32,768) 2 (2048) 20 0 to +70 3.0 - 3.6 pdip-40 z8f3201pm020sc z8 encore! ? 32 (32,768) 2 (2048) 20 0 to +70 3.0 - 3.6 lqfp-44 z8f3201an020sc z8 encore! ? 32 (32,768) 2 (2048) 20 0 to +70 3.0 - 3.6 plcc-44 z8f3201vn020sc z8 encore! ? 32 (32,768) 2 (2048) 20 0 to +70 3.0 - 3.6 lqfp-64 z8f3202ar020sc z8 encore! ? 32 (32,768) 2 (2048) 20 0 to +70 3.0 - 3.6 plcc-68 z8f3202vs020sc z8 encore! ? with 48kb flash, st andard temperature z8 encore! ? 48 (49,152) 4 (4096) 20 0 to +70 3.0 - 3.6 pdip-40 z8f4801pm020sc z8 encore! ? 48 (49,152) 4 (4096) 20 0 to +70 3.0 - 3.6 lqfp-44 z8f4801an020sc z8 encore! ? 48 (49,152) 4 (4096) 20 0 to +70 3.0 - 3.6 plcc-44 z8f4801vn020sc z8 encore! ? 48 (49,152) 4 (4096) 20 0 to +70 3.0 - 3.6 lqfp-64 z8f4802ar020sc z8 encore! ? 48 (49,152) 4 (4096) 20 0 to +70 3.0 - 3.6 plcc-68 z8f4802vs020sc z8 encore! ? 48 (49,152) 4 (4096) 20 0 to +70 3.0 - 3.6 qfp-80 z8f4803ft020sc
ps017611-0406 ordering information z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 212 z8 encore! with 64kb flas h, standard temperature z8 encore! ? 64 (65,536) 4 (4096) 20 0 to +70 3.0 - 3.6 pdip-40 z8f6401pm020sc z8 encore! ? 64 (65,536) 4 (4096) 20 0 to +70 3.0 - 3.6 lqfp-44 z8f6401an020sc z8 encore! ? 64 (65,536) 4 (4096) 20 0 to +70 3.0 - 3.6 plcc-44 z8f6401vn020sc z8 encore! ? 64 (65,536) 4 (4096) 20 0 to +70 3.0 - 3.6 lqfp-64 z8f6402ar020sc z8 encore! ? 64 (65,536) 4 (4096) 20 0 to +70 3.0 - 3.6 plcc-68 z8f6402vs020sc z8 encore! ? 64 (65,536) 4 (4096) 20 0 to +70 3.0 - 3.6 qfp-80 z8f6403ft020sc z8 encore! ? with 16kb flash, extended temperature z8 encore! ? 16 (16,384) 2 (2048) 20 -40 to +105 3.0 - 3.6 pdip-40 z8f1601pm020ec z8 encore! ? 16 (16,384) 2 (2048) 20 -40 to +105 3.0 - 3.6 lqfp-44 z8f1601an020ec z8 encore! ? 16 (16,384) 2 (2048) 20 -40 to +105 3.0 - 3.6 plcc-44 z8f1601vn020ec z8 encore! ? 16 (16,384) 2 (2048) 20 -40 to +105 3.0 - 3.6 lqfp-64 z8f1602ar020ec z8 encore! ? 16 (16,384) 2 (2048) 20 -40 to +105 3.0 - 3.6 plcc-68 z8f1602vs020ec z8 encore! ? with 24kb flash, extended temperature z8 encore! ? 24 (24,576) 2 (2048) 20 -40 to +105 3.0 - 3.6 pdip-40 z8f2401pm020ec z8 encore! ? 24 (24,576) 2 (2048) 20 -40 to +105 3.0 - 3.6 lqfp-44 z8f2401an020ec z8 encore! ? 24 (24,576) 2 (2048) 20 -40 to +105 3.0 - 3.6 plcc-44 z8f2401vn020ec z8 encore! ? 24 (24,576) 2 (2048) 20 -40 to +105 3.0 - 3.6 lqfp-64 Z8F2402AR020EC z8 encore! ? 24 (24,576) 2 (2048) 20 -40 to +105 3.0 - 3.6 plcc-68 z8f2402vs020ec z8 encore! with 32kb flash, extended temperature z8 encore! ? 32 (32,768) 2 (2048) 20 -40 to +105 3.0 - 3.6 pdip-40 z8f3201pm020ec z8 encore! ? 32 (32,768) 2 (2048) 20 -40 to +105 3.0 - 3.6 lqfp-44 z8f3201an020ec z8 encore! ? 32 (32,768) 2 (2048) 20 -40 to +105 3.0 - 3.6 plcc-44 z8f3201vn020ec z8 encore! ? 32 (32,768) 2 (2048) 20 -40 to +105 3.0 - 3.6 lqfp-64 z8f3202ar020ec z8 encore! ? 32 (32,768) 2 (2048) 20 -40 to +105 3.0 - 3.6 plcc-68 z8f3202vs020ec table 128. ordering in formation (continued) part flash kb (bytes) ram kb (bytes) max. speed (mhz) temp ( 0 c) voltage (v) package part number
ps017611-0406 ordering information z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 213 contact zilog?s worldwide customer support center for more information on ordering the z8 encore! ? . the customer support center is open from 7 a.m. to 7 p.m. pacific time. the customer support toll-free number for zilog is 1-877-zilogcs (1-877-945-6427). for z8 encore! ? the customer support toll-free numb er is 1-866-498-3636. the fax num- ber for the customer support center is 1-603- 316-0345. customers can also gain access to customer support using the zilog website. z8 encore! ? has its own web page at www.zilog.com/z8encore . for customer service, navigate your browser to: ? http://register.zilog.com/l ogin.asp?login = servicelogin for technical support, navigate your browser to: ? http://register.zilog.com/login.asp?login = supportlogin z8 encore! ? with 48kb flash, extended temperature z8 encore! ? 48 (49,152) 4 (4096) 20 -40 to +105 3.0 - 3.6 pdip-40 z8f4801pm020ec z8 encore! ? 48 (49,152) 4 (4096) 20 -40 to +105 3.0 - 3.6 lqfp-44 z8f4801an020ec z8 encore! ? 48 (49,152) 4 (4096) 20 -40 to +105 3.0 - 3.6 plcc-44 z8f4801vn020ec z8 encore! ? 48 (49,152) 4 (4096) 20 -40 to +105 3.0 - 3.6 lqfp-64 z8f4802ar020ec z8 encore! ? 48 (49,152) 4 (4096) 20 -40 to +105 3.0 - 3.6 plcc-68 z8f4802vs020ec z8 encore! ? 48 (49,152) 4 (4096) 20 -40 to +105 3.0 - 3.6 qfp-80 z8f4803ft020ec z8 encore! ? with 64kb flash, extended temperature z8 encore! ? 64 (65,536) 4 (4096) 20 -40 to +105 3.0 - 3.6 pdip-40 z8f6401pm020ec z8 encore! ? 64 (65,536) 4 (4096) 20 -40 to +105 3.0 - 3.6 lqfp-44 z8f6401an020ec z8 encore! ? 64 (65,536) 4 (4096) 20 -40 to +105 3.0 - 3.6 plcc-44 z8f6401vn020ec z8 encore! ? 64 (65,536) 4 (4096) 20 -40 to +105 3.0 - 3.6 lqfp-64 z8f6402ar020ec z8 encore!v 64 (65,536) 4 (4096) 20 -40 to +105 3.0 - 3.6 plcc-68 z8f6402vs020ec z8 encore! ? 64 (65,536) 4 (4096) 20 -40 to +105 3.0 - 3.6 qfp-80 z8f6403ft020ec z8 encore! ? development tools z8 encore! ? developer kit z8encore000zco table 128. ordering in formation (continued) part flash kb (bytes) ram kb (bytes) max. speed (mhz) temp ( 0 c) voltage (v) package part number
ps017611-0406 ordering information z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 214 for valuable informa tion about hardware and software development tools, visit the zilog web site at www.zilog.com . the latest released version of zds can be down- loaded from this site. part number description zilog part numbers consist of a number of components, as indicated in the following examples: example: part number z8f06401an020sc is an 8-bit microcontroller product in an lqfp package, using 44 pins, operating with a maximum 20mhz external clock frequency over a 0oc to +70oc temperature range and built using the plastic-standard environmental flow. zilog base products z8 zilog 8-bit microcontroller product f6 flash memory 64 program memory size 01 device number a package npin count 020 speed s temperature range c environmental flow packages a = lqfp s = soic h = ssop p = pdip v = plcc f = qfp pin count h = 20 pins j = 28 pins m = 40 pins n = 44 pins r = 64 pins s = 68 pins t = 80 pins speed 020 = 20mhz temperature s = 0oc to +70oc e = -40oc to +105oc environmental flow c = plastic-standard
ps017611-0406 document information z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 215 precharacterization product the product represented by this document is newly introduced and zilog has not com- pleted the full characterization of the prod uct. the document states what zilog knows about this product at this time, but additi onal features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and charact erization work. in addition, zilog cautions that delivery might be uncertain at times, due to start-up yield issues. zilog, inc. 532 race street san jose, ca 95126 telephone (408) 558-8500 fax 408 558-8300 internet: www.zilog.com document information document number description the document control number that appears in the footer on each page of this document contains unique identifying attributes, as indicated in the following table: ps product specification 0176 unique document number 01 revision number 0702 month and year published
ps017611-0406 customer feedback form z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 216 customer feedback form the z8 encore!? pr oduct specification if you experience any problems whil e operating this product, or if you note any in accuracies while reading this product specification, please copy and complete this form, then mail or fax it to zilog (see return information , below). we also welcome your suggestions! customer information product information return information zilog 532 race street san jose, ca 95126 fax: (408) 558-8536 email: tools@zilog.com name country company phone address fax city/state/zip e-mail part #, serial #, board fab #, or rev. # software version document number host computer description/type
ps017611-0406 customer feedback form z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 217 problem description or suggestion provide a complete description of th e problem or your suggestion. if yo u are reporting a specific problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________ ______________________________________________________________________________________
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 218 index symbols # 185 % 185 @ 185 numerics 10-bit adc 4 40-lead plastic dual-inline package 206 44-lead low-profile quad flat package 207 44-lead plastic lead chip carrier package 207 64-lead low-profile quad flat package 208 68-lead plastic lead chip carrier package 209 80-lead quad flat package 210 a absolute maximum ratings 167 ac characteristics 172 adc 187 architecture 132 automatic power-down 133 block diagram 133 continuous conversion 134 control register 135 control register definitions 135 data high byte register 137 data low bits register 137 dma control 135 electrical characteristics and timing 174 operation 133 single-shot conversion 133 adcctl register 135 adcdh register 137 adcdl register 137 adcx 187 add 187 add - extended addressing 187 add with carry 187 add with carry - extended addressing 187 additional symbols 185 address space 17 addx 187 analog signals 14 analog-to-digital converter (adc) 132 and 190 andx 190 arithmetic instructions 187 assembly language programming 182 assembly language syntax 183 b b 185 b 184 baud rate generator, uart 85 bclr 188 binary number suffix 185 bit 188 bit 184 clear 188 manipulation instructions 188 set 188 set or clear 188 swap 188 test and jump 190 test and jump if non-zero 190 test and jump if zero 190 bit jump and test if non-zero 190 bit swap 191 block diagram 3 block transfer instructions 188 brk 190 bset 188 bswap 188 , 191 btj 190 btjnz 190 btjz 190 c call procedure 190 capture mode 71 capture/compare mode 71
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 219 cc 184 ccf 189 characteristics, electrical 167 clear 189 clock phase (spi) 102 clr 189 com 190 compare 71 compare - extended addressing 187 compare mode 71 compare with carry 187 compare with carry - extended addressing 187 complement 190 complement carry flag 188 , 189 condition code 184 continuous assertion interrupt sources 47 continuous conversion (adc) 134 continuous mode 70 control register definition, uart 86 control register, i2c 119 counter modes 70 cp 187 cpc 187 cpcx 187 cpu and peripheral overview 3 cpu control instructions 189 cpx 187 customer feedback form 216 customer information 216 customer service 213 d da 184 , 187 data memory 19 data register, i2c 118 dc characteristics 169 debugger, on-chip 151 dec 187 decimal adjust 187 decrement 187 decrement and jump non-zero 190 decrement word 187 decw 187 destination operand 185 device, port availability 33 di 189 direct address 184 direct memory access controller 122 disable interrupts 189 djnz 190 dma address high nibble register 126 configuring for dma_adc data transfer 124 confiigurting dma0-1 data transfer 123 control of adc 135 control register 124 control register definitions 124 controller 5 dma_adc address register 128 dma_adc control register 130 dma_adc operation 123 end address low byte register 128 i/o address register 125 operation 122 start/current address low byte register 127 status register 131 dmaa_stat register 131 dmaactl register 130 dmaxctl register 124 dmaxend register 128 dmaxh register 126 dmaxi/o address (dmaxio) 126 dmaxio register 126 dmaxstart register 128 document number description 215 dst 185 e ei 189 electrical characteristics 167 adc 174 flash memory and timing 173 gpio input data sample timing 176 watch-dog timer 174 enable interrupt 189 er 184
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 220 extended addressing register 184 external pin reset 29 ez8 cpu features 3 ez8 cpu instruction classes 187 ez8 cpu instruction notation 183 ez8 cpu instruction set 182 ez8 cpu instruction summary 191 f fctl register 144 features, z8 encore! ? 1 first opcode map 204 flags 185 flags register 185 flash controller 4 option bit address space 148 option bit configuration - reset 148 program memory address 0000h 149 program memory address 0001h 150 flash memory 138 arrangement 139 byte programming 142 code protection 141 configurations 138 control register definitions 144 controller bypass 143 electrical characteristics and timing 173 flash control register 144 flash option bits 142 flash status register 145 flow chart 140 frequency high and low byte registers 147 mass erase 143 operation 139 operation timing 141 page erase 143 page select register 146 fps register 146 fstat register 145 g gated mode 71 general-purpose i/o 33 gpio 4 , 33 alternate functions 34 architecture 34 control register definitions 36 input data sample timing 176 interrupts 36 port a-h address registers 37 port a-h alternate function sub-registers 39 port a-h control registers 38 port a-h data direction sub-registers 39 port a-h high drive enable sub-registers 41 port a-h input data registers 42 port a-h output control sub-registers 40 port a-h output data registers 43 port a-h stop mode recovery sub-registers 41 port availability by device 33 port input timing 176 port output timing 177 h h 185 halt 189 halt mode 31 , 189 hexadecimal number prefix/suffix 185 i i 2 c 4 10-bit address read transaction 116 10-bit address transaction 114 10-bit addressed slave data transfer format 114 10-bit receive data format 116 7-bit address transaction 112 7-bit address, reading a transaction 115 7-bit addressed slave data transfer format 113 7-bit receive data transfer format 115 baud high and low byte registers 121 c status register 118 control register definitions 118
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 221 controller 111 controller signals 13 interrupts 112 operation 111 sda and scl signals 111 stop and start conditions 112 i2cbrh register 121 i2cbrl register 121 i2cctl register 119 i2cdata register 118 i2cstat register 118 im 184 immediate data 184 immediate operand prefix 185 inc 187 increment 187 increment word 187 incw 187 indexed 184 indirect address prefix 185 indirect register 184 indirect register pair 184 indirect working register 184 indirect working register pair 184 infrared encoder/decoder (irda) 95 instruction set, ez8 cpu 182 instructions adc 187 adcx 187 add 187 addx 187 and 190 andx 190 arithmetic 187 bclr 188 bit 188 bit manipulation 188 block transfer 188 brk 190 bset 188 bswap 188 , 191 btj 190 btjnz 190 btjz 190 call 190 ccf 188 , 189 clr 189 com 190 cp 187 cpc 187 cpcx 187 cpu control 189 cpx 187 da 187 dec 187 decw 187 di 189 djnz 190 ei 189 halt 189 inc 187 incw 187 iret 190 jp 190 ld 189 ldc 189 ldci 188 , 189 lde 189 ldei 188 ldx 189 lea 189 load 189 logical 190 mult 187 nop 189 or 190 orx 190 pop 189 popx 189 program control 190 push 189 pushx 189 rcf 188 , 189 ret 190 rl 191 rlc 191 rotate and shift 191 rr 191
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 222 rrc 191 sbc 188 scf 188 , 189 sra 191 srl 191 srp 189 stop 189 sub 188 subx 188 swap 191 tcm 188 tcmx 188 tm 188 tmx 188 trap 190 watch-dog timer refresh 189 xor 190 xorx 190 instructions, ez8 classes of 187 interrupt control register 56 interrupt controller 5 , 44 architecture 44 interrupt assertion types 47 interrupt vectors and priority 47 operation 46 register definitions 48 interrupt edge select register 54 interrupt port select register 55 interrupt request 0 register 48 interrupt request 1 register 49 interrupt request 2 register 50 interrupt return 190 interrupt vector listing 44 interrupts not acknowledge 112 receive 112 spi 105 transmit 112 uart 85 introduction 1 ir 184 ir 184 irda architecture 95 block diagram 95 control register definitions 98 jitter 98 operation 96 receiving data 97 transmitting data 96 iret 190 irq0 enable high and low bit registers 51 irq1 enable high and low bit registers 52 irq2 enable high and low bit registers 53 irr 184 irr 184 j jitter 98 jp 190 jump, conditional, relative, and relative conditional 190 l ld 189 ldc 189 ldci 188 , 189 lde 189 ldei 188 , 189 ldx 189 lea 189 load 189 load constant 188 load constant to/from program memory 189 load constant with auto-increment addresses 189 load effective address 189 load external data 189 load external data to/fro m data memory and auto- increment addresses 188 load external to/from data memory and auto-incre- ment addresses 189 load instructions 189 load using extended addressing 189 logical and 190 logical and/extended addressing 190 logical exclusive or 190
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 223 logical exclusive or/extended addressing 190 logical instructions 190 logical or 190 logical or/extended addressing 190 low power modes 31 lqfp 44 lead 207 64 lead 208 m master interrupt enable 46 master-in, slave-out and-in 101 memory data 19 program 18 miso 101 mode capture 71 capture/compare 71 continuous 70 counter 70 gated 71 one-shot 70 pwm 70 modes 71 mosi 101 mult 187 multiply 187 multiprocessor mode, uart 84 n nop (no operation) 189 not acknowledge interrupt 112 notation b 184 cc 184 da 184 er 184 im 184 ir 184 ir 184 irr 184 irr 184 p 184 r 184 r 184 ra 184 rr 184 rr 184 vector 184 x 184 notational shorthand 184 o ocd architecture 151 auto-baud detector/generator 154 baud rate limits 154 block diagram 151 breakpoints 155 commands 156 control register 161 data format 154 dbg pin to rs-232 interface 152 debug mode 153 debugger break 190 interface 152 serial errors 155 status register 162 timing 178 watchpoint address register 164 watchpoint control register 163 watchpoint data register 164 watchpoints 155 ocd commands execute instruction (12h) 160 read data memory (0dh) 160 read ocd control register (05h) 158 read ocd revision (00h) 157 read ocd status register (02h) 157 read program counter (07h) 158 read program memory (0bh) 159 read program memory crc (0eh) 160 read register (09h) 158 read runtime counter (03h) 157
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 224 read watchpoint (21h) 161 step instruction (10h) 160 stuff instruction (11h) 160 write data memory (0ch) 159 write ocd control register (04h) 158 write program counter (06h) 158 write program memory (0ah) 159 write register (08h) 158 write watchpoint (20h) 161 on-chip debugger 5 on-chip debugger (ocd) 151 on-chip debugger signals 14 on-chip oscillator 165 one-shot mode 70 opcode map abbreviations 203 cell description 202 first 204 second after 1fh 205 or 190 ordering information 211 orx 190 oscillator signals 14 p p 184 packaging lqfp 44 lead 207 64 lead 208 pdip 206 plcc 44 lead 207 68 lead 209 qfp 210 part number description 214 part selection guide 2 pc 185 pdip 206 peripheral ac and dc el ectrical characteristics 173 phase=0 timing (spi) 103 phase=1 timing (spi) 104 pin characteristics 15 plcc 44 lead 207 68-lead 209 polarity 184 pop 189 pop using extended addressing 189 popx 189 port availability, device 33 port input timing (gpio) 176 port output timing, gpio 177 power supply signals 15 power-down, automatic (adc) 133 power-on and voltage brown-out 173 power-on reset (por) 27 problem description or suggestion 217 product information 216 program control instructions 190 program counter 185 program memory 18 push 189 push using extended addressing 189 pushx 189 pwm mode 70 pxaddr register 37 pxctl register 38 q qfp 210 r r 184 r 184 ra, register address 184 rcf 188 , 189 receive 10-bit data format (i2c) 116 7-bit data transfer format (i2c) 115 irda data 97 receive interrupt 112 receiving uart data-dma controller 83 receiving uart data-interrupt-driven method 82 receiving uart data-polled method 82
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 225 register 109 , 126 , 184 adc control (adcctl) 135 adc data high byte (adcdh) 137 adc data low bits (adcdl) 137 baud low and high byte (i2c) 121 baud rate high and low byte (spi) 110 control (spi) 107 control, i2c 119 data, spi 106 dma status (dmaa_stat) 131 dma_adc address 128 dma_adc control dmaactl) 130 dmax address high nibble (dmaxh) 126 dmax control (dmaxctl) 124 dmax end/address low byte (dmaxend) 128 dmax start/current address low byte register (dmaxstart) 128 flash control (fctl) 144 flash high and low byte (ffreqh and freeql) 147 flash page select (fps) 146 flash status (fstat) 145 gpio port a-h address (pxaddr) 37 gpio port a-h alternate function sub-registers 39 gpio port a-h control address (pxctl) 38 gpio port a-h data direction sub-registers 39 i2c baud rate high (i2cbrh) 121 i2c control (i2cctl) 119 i2c data (i2cdata) 118 i2c status 118 i2c status (i2cstat) 118 i2cbaud rate low (i2cbrl) 121 mode, spi 109 ocd control 161 ocd status 162 ocd watchpoint address 164 ocd watchpoint control 163 ocd watchpoint data 164 spi baud rate high byte (spibrh) 110 spi baud rate low byte (spibrl) 110 spi control (spictl) 107 spi data (spidata) 106 spi status (spistat) 108 status, i2c 118 status, spi 108 uartx baud rate high byte (uxbrh) 91 uartx baud rate low byte (uxbrl) 92 uartx control 0 (uxctl0) 89 uartx control 1 (uxctl1) 90 uartx receive data (uxrxd) 87 uartx status 0 (uxstat0) 87 uartx status 1 (uxstat1) 89 uartx transmit data (uxtxd) 86 watch-dog timer control (wdtctl) 75 watch-dog timer reload high byte (wdth) 76 watch-dog timer reload low byte (wdtl) 77 watch-dog timer reload upper byte (wdtu) 76 register file 17 register file address map 20 register pair 184 register pointer 185 reset and stop mode characteristics 25 and stop mode recovery 25 carry flag 188 controller 5 sources 26 ret 190 return 190 return information 216 rl 191 rlc 191 rotate and shift instructions 191 rotate left 191 rotate left through carry 191 rotate right 191 rotate right through carry 191 rp 185 rr 184 , 191 rr 184 rrc 191 s sbc 188 scf 188 , 189 sck 101
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 226 sda and scl (irda) signals 111 second opcode map after 1fh 205 serial clock 101 serial peripheral interface (spi) 99 set carry flag 188 , 189 set register pointer 189 shift right arithmetic 191 shift right logical 191 signal descriptions 13 single assertion (pulse) interrupt sources 47 single-shot conversion (adc) 133 sio 5 slave data transfer formats (i2c) 114 slave select 102 software trap 190 source operand 185 sp 185 spi architecture 99 baud rate generator 105 baud rate high and low byte register 110 clock phase 102 configured as slave 100 control register 107 control register definitions 106 data register 106 error detection 105 interrupts 105 mode fault error 105 mode register 109 multi-master operation 104 operation 100 overrun error 105 signals 101 single master, multiple slave system 100 single master, single slave system 99 status register 108 timing, phase = 0 103 timing, phase=1 104 spi controller signals 13 spi mode (spimode) 109 spibrh register 110 spibrl register 110 spictl register 107 spidata register 106 spimode register 109 spistat register 108 sra 191 src 185 srl 191 srp 189 ss, spi signal 101 stack pointer 185 status register, i2c 118 stop 189 stop mode 31 , 189 stop mode recovery sources 29 using a gpio port pin transition 30 using watch-dog timer time-out 29 sub 188 subtract 188 subtract - extended addressing 188 subtract with carry 188 subtract with carry - extended addressing 188 subx 188 swap 191 swap nibbles 191 symbols, additional 185 system and short resets 26 t tcm 188 tcmx 188 technical support 213 test complement under mask 188 test under mask 188 timer signals 14 timers 5 , 57 architecture 57 block diagram 58 capture mode 62 , 71 capture/compare mode 65 , 71 compare mode 63 , 71 continuous mode 59 , 70 counter mode 60 counter modes 70
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 227 gated mode 64 , 71 one-shot mode 58 , 70 operating mode 58 pwm mode 61 , 70 reading the timer count values 66 reload high and low byte registers 67 timer control register definitions 66 timer output signal operation 66 timers 0-3 control registers 70 high and low byte registers 66 , 69 tm, tmx 188 tools, hardware and software 214 transmit irda data 96 transmit interrupt 112 transmitting uart data-polled method 80 transmitting uart data-int errupt-driven method 81 trap 190 u uart 4 architecture 78 asynchronous data format without/with parity 80 baud rate generator 85 baud rates table 93 control register definitions 86 controller signals 14 data format 79 interrupts 85 multiprocessor mode 84 receiving data us ing dma controller 83 receiving data using interrupt-driven method 82 receiving data using the polled method 82 transmitting data using the interrupt-driven method 81 transmitting data using the polled method 80 x baud rate high and low registers 91 x control 0 and control 1 registers 89 x status 0 and status 1 registers 87 uxbrh register 91 uxbrl register 92 uxctl0 register 89 uxctl1 register 90 uxrxd register 87 uxstat0 register 87 uxstat1 register 89 uxtxd register 86 v vector 184 voltage brown-out reset (vbr) 27 w watch-dog timer approximate time-out delays 72, 73 cntl 28 control register 75 electrical characteristics and timing 174 interrupt in normal operation 73 interrupt in stop mode 73 operation 72 refresh 73 , 189 reload unlock sequence 74 reload upper, high and low registers 76 reset 28 reset in normal operation 74 reset in stop mode 74 time-out response 73 wdtctl register 75 wdth register 76 wdtl register 77 working register 184 working register pair 184 wtdu register 76 x x 184 xor 190 xorx 190
ps017611-0406 index z8f640x/z8f480x/z8f320x/z8f240x/z8f160x z8 encore! ? 228 z z8 encore! block diagram 3 features 1 introduction 1 part selection guide 2

▲Up To Search▲

Price & Availability of Z8F2402AR020EC

	To Download Z8F2402AR020EC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .